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| Data Sheet C-5e NETWORK PROCESSOR SILICON REVISION A1 Freescale Semiconductor, Inc... C5ENPA1-DS/D Rev 03 PRELIMINARY Freescale Semiconductor, Inc... Data Sheet Freescale Semiconductor, Inc... C-5e Network Processor Silicon Revision A1 Pr C5ENPA1-DS/D Rev 03 el im in ar y Freescale Semiconductor, Inc... C5ENPA1-DS/D Rev 03 CONTENTS Freescale Semiconductor, Inc... About This Guide Guide Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using PDF Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 14 16 16 17 CHAPTER 1 Functional Description Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Massive Processing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Functional Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 20 22 23 23 24 24 25 26 CHAPTER 2 Signal Descriptions Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 30 30 31 32 34 34 35 03 6 CONTENTS Freescale Semiconductor, Inc... Gigabit Ethernet and Fibre Channel TBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SONET OC-3 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SONET OC-12 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU SRAM (Internal Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU to Q-5 TMC (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDcode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 39 40 42 42 43 44 47 48 52 54 55 56 57 58 58 59 69 69 69 69 69 71 71 72 CHAPTER 3 Electrical Specifications Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Package Conduction Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heat Sink Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 74 75 76 77 77 78 79 81 82 C CONTENTS 7 Freescale Semiconductor, Inc... CP Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DS1/DS3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10/100 Ethernet Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications . . . . . . . . . . . . . . . . . . 85 OC-3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 OC-12 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Executive Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MDIO Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Low Speed Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PROM Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Fabric Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 BMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TLU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 QMU SRAM (Internal Mode) Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 QMU to Q-5 (External Mode) Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CHAPTER 4 Mechanical Specifications Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 106 106 107 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 03 Freescale Semiconductor, Inc... 8 CONTENTS C C5ENPA1-DS/D Rev 03 LIST OF FIGURES Freescale Semiconductor, Inc... 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C-5e Network Processor Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Locations (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Cell Design That Can Be Used for Both Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Bringup Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Package Cross Section View with Several Heat Sink Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Package with Heat Sink Mounted to the Printed Circuit Board. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Test Loading Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 QMU SRAM (Internal Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 QMU to Q-5 (External Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 C-5e Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 C-5e Network Processor BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 C-5e Network Processor BGA Package (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 03 Freescale Semiconductor, Inc... 10 LIST OF FIGURES C C5ENPA1-DS/D Rev 03 LIST OF TABLES Freescale Semiconductor, Inc... 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Navigating Within a PDF Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C-5e Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C-Port Silicon Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TLU SRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . . . . . . 35 Gigabit Ethernet (GMII/MII) Signals One Cluster Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PROM Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Fabric Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Utopia1*, 2, 3 ATM Mode, C-5e Network Processor to Fabric Interface Pin Mapping . . . . . . 49 Utopia1*, 2, 3 PHY Mode, C-5e Network Processor to Fabric Interface Pin Mapping . . . . . . . 49 PRIZMA Mode, C-5e Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . . . 50 Power X(CSIX-L0) Mode, C-5e Network Processor to Fabric Interface Pin Mapping . . . . . . . . 50 CSIX-L1 Mode, C-5e Network to Fabric Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 51 BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 QMU SRAM (Internal Mode) Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 QMU to Q-5 (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Power Supply Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . . . . 58 03 12 LIST OF TABLES 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Signals Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 JTAG Internal Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 JTAG Identification Code and Its Subcomponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 C-5e Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C-5e Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .74 C-5e Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 C-5e Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 C-5e Network Processor Power and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 QMU SRAM (Internal Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . 100 QMU to Q-5 (External Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Signal Groups in QMU to Q-5 (External Mode) Timimg Diagrams . . . . . . . . . . . . . . . . . . . . . . . 102 Package Measurements (Reference Figure 28, Figure 29 and Figure 30 for Symbols). . . . 106 C-5e Network Processor Marking Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Freescale Semiconductor, Inc... C C5ENPA1-DS/D Rev 03 ABOUT THIS GUIDE Freescale Semiconductor, Inc... Guide Overview The C-5e Network Processor Data Sheet describes hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. This document contains information on a pre-production product. Specifications and information herein are subject to change without notice. This guide assumes a good understanding of the C-5eTM Network Processor (NP) architecture. See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D) for more detail about the hardware. This guide also assumes good working knowledge of the C-Ware Software Toolset. This guide covers the following topics: * * * * Functional Description Signal Descriptions Electrical Specifications Mechanical Specifications 03 14 ABOUT THIS GUIDE Data Sheet Classifications Table 1 describes the Data Sheet classifications of Advance, Preliminary, and Production. Table 1 Data Sheet Classifications CLASSIFICATION DESCRIPTION Advance Information Freescale Semiconductor, Inc... Used to advise customers of the proposed addition to the product line. This document will typically contain some useful information including interfacing with the user's system and some specifications. The goal of this document is to allow customers to begin designs but with expectation of changes. Specification details may be changed later without notice. Describes pre-production or first production devices and is usually indicative of production stage performance. Minor changes should be expected as characteristic spreads become better controlled. Specification details may be changed slightly without notice, but the customer can design their product based on this data sheet. Defines the long-term specified production limits based on fully characterized data. It includes a disclaimer to allow improvements in specifications and modifications that do not affect form, fit or function in original applications; if absolute maximum ratings are changed, they should improve rather than downgrade. Preliminary Information Production Data Using PDF Documents Electronic documents are provided as PDF files. Open and view them using the Adobe(R) Acrobat(R) Reader application, version 3.0 or later. If necessary, download the Acrobat Reader from the Adobe Systems, Inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html PDF files offer several ways for moving among the document's pages, as follows: * To move quickly from section to section within the document, use the Acrobat bookmarks that appear on the left side of the Acrobat Reader window. The bookmarks provide an expandable outline view of the document's contents. To display the document's Acrobat bookmarks, press the "Display both bookmarks and page" button on the Acrobat Reader tool bar. To move to the referenced page of an entry in the document's Contents or Index, click on the entry itself, each of which is hyperlinked. To follow a cross-reference to a heading, figure, or table, click the blue text. * * C Using PDF Documents 15 * To move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the Acrobat Reader navigation buttons shown in this figure: Beginning of document End of Previous or next hyperlink Previous Next page Freescale Semiconductor, Inc... Table 2 summarizes how to navigate within an electronic document. Table 2 Navigating Within a PDF Document TO NAVIGATE THIS WAY CLICK THIS Move from section to section within the document. Move to an entry in the Table of Contents. Move to an entry in the Index. Move to an entry in the List of Figures or List of Tables. A bookmark on the left side of the Acrobat Reader window The entry itself The page number The Figure or Table number Follow a cross-reference (highlighted in blue The cross-reference text text). Move page by page. Move to the beginning or end of the document. The appropriate Acrobat Reader navigation buttons The appropriate Acrobat Reader navigation buttons Move backward or forward among a series of The appropriate Acrobat Reader navigation hyperlinks you have selected. buttons 03 16 ABOUT THIS GUIDE Guide Conventions The following visual elements are used throughout this guide, where applicable: This icon and text designates information of special note. Freescale Semiconductor, Inc... Warning: This icon and text indicate a potentially dangerous procedure. Instructions contained in the warnings must be followed. Warning: This icon and text indicate a procedure where the reader must take precautions regarding laser light. This icon and text indicate the possibility of electrostatic discharge (ESD) in a procedure that requires the reader to take the proper ESD precautions. Revision History Table 3 provides details about changes made for each revision of this guide. Table 3 C-5e Network Processor Data Sheet Revision History REVISION DATE CST REVISION CDS REVISION CHANGES November 8, 2002 2.2 2.0 Added information about optional capacitors, nominal values for recommended operating conditions, and updated package measurement values. C Related Product Documentation 17 Related Product Documentation Table 4 lists the user and reference documentation for Motorola `s C-Port silicon documentation set. Table 4 C-Port Silicon Documentation Set DOCUMENT SUBJECT DOCUMENT NAME PURPOSE DOCUMENT ID Freescale Semiconductor, Inc... Processor C-5 Network Processor Architecture Guide Information C-5 Network Processor Data Sheet C-5e/C-3e Network Processor Architecture Guide C-5e Network Processor Data Sheet C-3e Network Processor Data Sheet C-5 Network Processor to C-5e Network Processor Comparison Delta Document M-5 Channel Adapter Architecture Guide M-5 Channel Adapter Data Sheet Q-5/Q-3 Traffic Management Coprocessor Architecture Guide Q-5 Traffic Management Coprocessor Data Sheet Describes the full architecture of the C-5 network processor. Describes hardware design specifications for the C-5 network processor. C5NPARCH-RM/D C5NPDATA-DS/D Describes the full architecture of the C-5e and C-3e C5EC3EARCH-RM/D network processors. Describes hardware design specifications for the C-5e network processor. Describes hardware design specifications for the C-3e network processor. Describes key architectural features of the C-5e, and highlights main differences between C-5 and C-5e. Describes the full architecture of the M-5 channel adapter. Describes hardware design specifications for the M-5 channel adapter. Describes the full architecture of the Q-5 and Q-3 traffic management coprocessor. Describes hardware design specifications for the Q-5 traffic management coprocessor. C5ENPA1-DS/D C3ENPA1-DS/D C5C5EDELTA-RM/D M5CAARCH-RM/D M5CA0-DS/D Q5Q3ARCH-RM/D Q5TMCA0-DS/D 03 Freescale Semiconductor, Inc... 18 ABOUT THIS GUIDE C C5ENPA1-DS/D Chapter 1 Rev 03 FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... Features Key features of the C-5eTM Network Processor (NP) are its massive processing capabilities and its high level of functional integration on one chip. Massive Processing Power * * * * * * * * Operating frequencies: up to 266MHz 5Gbps of bandwidth (for non-blocking throughput) More than 4,500MIPS of computing power (for adding services throughout the protocol stack) Up to 15 million packets per second transmitted at wire speed 17 programmable RISC Cores (for cell/packet forwarding) 32 programmable Serial Data Processors (for processing bit streams) Up to 133 million table lookups per second Three internal buses for 68Gbs of aggregate bandwidth 840 pin Ball Grid Array (BGA) package 16 Channel Processors including: - Embedded OC-3c , OC-12 , OC-12c SONET framers - Programmable MAC interface - RISC Cores - Programmable pin PHY interfaces High Functional Integration * * * * Embedded coprocessors for table lookup (classification), buffer management (payload control), and queue management (CoS/QoS implementation) Dedicated Fabric Processor and port 03 20 CHAPTER 1: FUNCTIONAL DESCRIPTION * * Block Diagram Embedded RISC Executive Processor Integrated 32bit 33/66MHz PCI bus interface The C-5eTM NP, has an architecture specifically designed for networking applications. The following sections describe each component of the C-5e NP. The main components of the C-5e NP are: Freescale Semiconductor, Inc... * * * * * * Channel Processors Executive Processor Fabric Processor Buffer Management Unit Table Lookup Unit Queue Management Unit The C-5e NP conforms with both SONET and SDH. Therefore, OC-3(STS-3/STM-1), OC-12 (STS-12/STM-4, and OC48 (STS-48/STM-16). Figure 1 shows a block diagram of the C-5e NP, including its potential external interfaces. For more information about the architecture of the C-5e NP, see the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D). C Block Diagram 21 Figure 1 C-5e Network Processor Block Diagram Q-5 (optional) SRAM SRAM Fabric External Host CPU (optional) External PROM (optional) SDRAM Control Logic (optional) Table Lookup Unit PCI Serial PROM Freescale Semiconductor, Inc... Fabric Processor Executive Processor Queue Mgmt Unit Buses (68Gbps Bandwidth) Buffer Mgmt Unit C-5e NP CP-0 Cluster PHY CP-1 CP-2 CP-3 CP-12 CP-13 CP-14 CP-15 Cluster Channel Processors Processor Boundary PHY PHY PHY PHY PHY PHY PHY PHY Interface Examples: 10/100 Ethernet Gigabit Ethernet - Aggregated OC-3 OC-12 1xOC-48c or 48x STS-1 with M-5 Companion Device 03 22 CHAPTER 1: FUNCTIONAL DESCRIPTION Channel Processors Freescale Semiconductor, Inc... The C-5e NP contains sixteen programmable Channel Processors (CPs) that receive, process, and transmit network data. The number of CPs per port is configurable, depending on the line interface. Typically one CP is assigned to each port for medium bandwidth applications (Fast Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an external multiplexor, for low bandwidth applications, such as DS1 to DS3. The C-5e NP's architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including: * * * * * * * * 10/100Mb Ethernet (RMII) 1Gb Ethernet (GMII and TBI) OC-3c OC-12 OC-48c (using various configurations with M-5 Channel Adapter) OC-48 (using various configurations with M-5 Channel Adapter) 100Mbit FibreChannel DS1/DS3, supported through the use of external framers/multiplexors The C-5e NP's programmability can also support a variety of special interfaces, such as various xDSL encapsulations and proprietary protocols. Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called Serial Data Processors (SDPs), that provide features such as Ethernet MAC and SONET/SDH framing, multichannel HDLC, and ATM cell delineation. This means you usually only need to include PHYs to complete the system. C Executive Processor 23 Executive Processor The Executive Processor (XP) serves as a centralized computing resource for the C-5e NP and manages the system interfaces. The XP performs conventional supervisory tasks in the C-5e NP, including: Freescale Semiconductor, Inc... * * * * * System Interfaces Reset and initialization of the C-5e NP Program loading and control of CPs Centralized exception handling Management of a host interface through the PCI Management of system interfaces (PCI, Serial Bus, PROM) The system interfaces to the XP are: * * PCI -- Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level shared resources. The PCI has both initiator and target capabilities. The PCI interface is typically connected to a host processor. Serial Bus Interface -- Provides a general purpose bi-directional, two-wire serial bus and I/O port that allows the C-5e NP to control external logic with either of two standard protocols: - The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of addressing and supports transfers up to 25MHz. - The low-speed protocol: uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. Software is used to select which protocol to use, by setting the appropriate bits in the Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is driven by the C-5e NP to indicate which protocol is being used (SPLD=0 indicates MDIO protocol; SPLD=1 indicates low-speed protocol). Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because of the pull-up resistor. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism. 03 24 CHAPTER 1: FUNCTIONAL DESCRIPTION * PROM Interface -- Allows the XP to boot from nonvolatile, flash memory. The PROM interface is a low-speed, serial I/O port that runs at 1/2 to 1/16 the core clock rate. The maximum PROM size addressable is 4MBytes, and must use a "by 16" part. External board logic is required to perform serial-to-parallel conversion for PROM address outputs and parallel-to-serial conversion for PROM data inputs. Freescale Semiconductor, Inc... Fabric Processor The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C-5e NP to interface to an application-specific switching solution internal to your design. The FP port supports the bidirectional transfer of segments from the C-5e NP to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. There are numerous parameters that can be configured within the FP to allow the interface to be adapted to different fabric protocols. The FP can be configured to conform to seven (7) different fabric interfaces that include: CSIX-L1, UTOPIA-1, -2, -3, PRIZMA, Power X(CSIX-L0), and UTOPIA3 like to M-5. The FP can be configured to run at any frequency up to 125MHz, with the receive and transmit data buses up to 32 bits wide. This allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 4000 Mbps full duplex bandwidth. Buffer Management Unit The Buffer Management Unit (BMU) interfaces the C-5e NP to external pipeline architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It is also used as second level storage in the XP memory hierarchy. The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine SECDED (single error correction-double error detection) ECC (error correction code) bits. The interface is compliant with the PC100 standard and operates at up to 133MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D) for more details). The C-5e NP non-configurable interface transfers four beats of data for each read and write using a sequential burst type. In addition, the C-5e NP uses an auto-refresh mode for the RAM's. C Table Lookup Unit 25 Some of these parameters are programmed into the SDRAMs' mode register and can be applied only once per power cycle. The ECC functionality can be enabled or disabled via configuration register writes. If needed, the interface can narrowed to 128bits by disabling ECC and providing board pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU supports SDRAM devices that use 12 address lines. Internal address calculation paths limit the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported. Freescale Semiconductor, Inc... Table Lookup Unit The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used for statistics accumulation and retrieval and as general data storage. The TLU simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and QoS lookup tasks. The C-5e NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules (at frequencies up to 133MHz) for storage of its tables. These modules allow implementation of tables with 225 x 64bit entries using 8Mbit SRAM technology. The maximum amount of memory supported by the TLU is 128MBytes in four banks, when SRAM technology supports 4M x 18pins parts. Table 5 TLU SRAM Configurations SRAM TECHNOLOGY MIN TABLE SIZE (ONE BANK) MAXIMUM TABLE SIZE (FOUR BANKS) 1Mbit (32k x 32pins) 2Mbit (64k x 32pins) 4Mbit (256k x 18pins) 8Mbit (512k x 18pins) 16Mbit (1M x 18pins) 32Mbit (2M x 18pins) 64Mbit (4M x 18pins) 256kBytes 512kBytes 2MBytes 4MBytes 8MBytes 16MBytes 32MBytes 1MBytes 2MBytes 8MBytes 16MBytes 32MBytes 64MBytes 128MBytes 03 26 CHAPTER 1: FUNCTIONAL DESCRIPTION Queue Management Unit The Queue Management Unit (QMU) autonomously manages a number of application-defined descriptor queues. It handles inter-CP and inter-C-5e NP descriptor flows by providing switching and buffering. It also performs descriptor replication for multicast applications. A number of up to 128 queues can be assigned to each CPRC for QoS-based services. The QMU provides a queuing engine internal to the chip and uses external SRAM to store the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and 16, 384 descriptor buffers. A descriptor buffer holds an application-defined "descriptor" , which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. The QMU's external SRAM interface uses ZBT synchronous SRAMs organized in a single bank of up to 128k, 32bit words. This interface runs at up to 175MHz frequency. The C-5e provides two modes for managing queues. They consist of: Freescale Semiconductor, Inc... * * Internal Mode (using the internal QMU only) External Mode (using the internal QMU and the external Q-5 Traffic Management Coprocessor) See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D), as well as, the Q-5/Q-3 Traffic Management Coprocessor Architecture Guide (part number Q5Q3ARCH-RM/D) for more details. C C5ENPA1-DS/D Chapter 2 Rev 03 SIGNAL DESCRIPTIONS Freescale Semiconductor, Inc... Signal Summary There are ten (10) functional groupings of signals in the C-5e Network Processor: * * * Clock -- 11 pins Channel Processors (CP0 - CP15) -- 16x7 = 112 pins Executive Processor (XP) -- 57 pins - PCI Interface -- 50 pins - PROM Interface -- 4 pins - Serial Bus Interface -- 2 pins - General System Interface -- 1 pin * * * * * * * Fabric Processor (FP) -- 80 pins Buffer Management Unit (BMU) -- 160 pins Table Lookup Unit (TLU) -- 99 pins Queue Management Unit (QMU) -- 59 pins Power -- 245 pins Test -- 14 pins No connection (NC) -- 3 pins Two (2) of the sections (CPs and FP) are configurable, depending on the type of device being implemented. 03 28 CHAPTER 2: SIGNAL DESCRIPTIONS Pinout Diagram The C-5e NP contains 840 pins. These pin numbers are referenced throughout the remaining chapter. Figure 2 shows the pin locations from the top view. In contrast, Figure 3 shows the pin locations from the bottom view. Figure 2 Pin Locations (Top View) 29 28 CP1_0 27 26 25 24 23 22 21 CP7_1 CP7_2 CP7_3 CP7_4 CP7_5 CP7_6 CP8_0 CPA_5 CPB_5 CPD_0 CPE_2 CPF_2 MD2 MD11 MD20 MD27 MD34 MD43 MD52 MD59 MD66 MD75 MD84 MD91 MD98 20 CP8_1 VDD33 CP8_2 CP8_3 GND CP8_4 CP8_5 VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 19 CP8_6 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND 18 17 16 15 14 13 12 11 FIN3 FIN4 FIN5 FIN6 FIN7 FIN8 FIN9 GND VDD GND VDD GND VDD GND VDD GND VDDT GND VDD GND VDDT GND QA13 QA14 QA15 QA16 10 FIN10 VDDF FIN11 FIN12 GND FIN13 FIN14 9 FIN15 FIN16 FIN17 FIN18 FIN19 FIN20 FIN21 8 FIN22 FIN23 FIN24 FIN25 FIN26 FIN27 FIN28 PIRDYX PRSTX PIDSEL 7 FIN29 FIN30 FIN31 GND FRXCTL0 6 FRXCTL3 GND FRXCTL4 5 PAD0 PAD5 PAD9 4 PAD1 PAD6 PAD10 PAD15 PAD19 PAD23 PAD28 PCBEX2 3 PAD2 PAD7 PAD11 VDD33 PAD20 PAD24 PAD29 2 PAD3 VDD33 PAD12 PAD16 GND PAD25 PAD30 1 PAD4 PAD8 PAD13 PAD17 PAD21 PAD26 PAD31 PPAR PSERRX SPDO TA15 TA8 TA1 TA0 TCLKI TD53 TD46 TD37 TD28 TD21 TD14 TD5 QD0 QD1 QD2 QD3 QD4 QD5 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 Freescale Semiconductor, Inc... AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A CP0_0 CP1_5 CP2_4 CP3_4 CP4_4 CP5_2 CP6_1 GND CP5_3 CP6_2 FOUT0 FOUT6 FOUT12 FOUT19 FOUT24 FOUT1 FOUT7 FOUT13 FOUT2 GND VDDF GND FOUT31 FTXCTL5 CP0_1 VDD33 CP1_6 CP2_5 CP3_5 CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP1_1 FOUT25 FTXCTL0 FTXCTL6 VDDF FTXCLK GND FIN0 FIN1 FIN2 VDDF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 CPREF CCLK6 CCLK7 GND JSO3 JSO5 JTRSTX 12 CP2_0 CP2_6 CP3_6 CP4_5 CP5_4 CP6_3 GND CP6_4 FOUT14 FOUT20 FOUT26 CP1_2 VDD33 CP3_0 CP4_0 CP4_6 GND CP1_3 CP1_4 FOUT8 FOUT15 FOUT21 FOUT27 FTXCTL1 VDDF FOUT28 FTXCTL2 FRXCTL5 PAD14 VDDF PAD18 CP2_1 CP3_1 CP4_1 VDD33 CP5_5 CP6_5 CP2_2 CP3_2 CP4_2 CP5_0 CP5_6 CP6_6 CP2_3 CP3_3 CP4_3 CP5_1 CP6_0 CP7_0 GND CPA_4 FOUT3 FOUT9 FOUT16 FOUT4 FOUT10 FOUT17 FOUT22 FOUT29 FTXCTL3 FOUT5 FOUT11 FOUT18 FOUT23 FOUT30 FTXCTL4 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 MDQM GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND MA11 VDDF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 MA5 MA4 MA3 MA2 MA1 MA0 JSO1 16 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND SCLK SCLKX VDD33 JSE VDDF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 CCLK0 CCLK1 CCLK2 JSO0 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND CCLK3 CCLK4 CCLK5 JSO2 VDD33 JHIGHZ JTDO 13 FRXCTL1 FRXCTL6 PAD22 FRXCTL2 FRXCLK GND PCLK PGNTX TA21 VDDT TA5 TWE1X TD61 GND TD50 TD43 TD34 VDDT TD18 TD11 TD1 VDDT QBCLKI PAD27 CP9_6 CPA_0 VDD33 CPA_1 CPA_2 CPA_3 CPA_6 GND VDD33 PTRDYX GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT TD4 QA9 GND QA10 PREQX PINTA PCBEX0 PCBEX1 VDD33 SIDA TA20 TA12 GND TWE0X TD60 TD57 VDDT TD42 TD33 TD25 GND TD10 TD0 QD30 GND QD31 QWEX GND QBCLKO 6 VDD33 PCBEX3 GND SPDI TA16 TA9 VDDT TCE0X TPAR0 TD54 GND TD38 TD29 TD22 VDDT TD6 QD6 QD7 GND QD8 QD9 VDDT QD10 2 CPB_0 CPB_1 CPB_2 VDD33 CPB_3 CPB_4 PSTOPX PDEVSELX PPERRX SICL TA19 TA11 TA4 TCE3X TPAR3 TD56 TD49 TD41 TD32 TD24 TD17 TD9 QD23 QD24 QD25 QD26 QD27 QD28 QD29 5 SPCK TA18 TA10 TA3 TCE2X TPAR2 TD55 TD48 TD40 TD31 TD23 TD16 TD8 QD16 QD17 QD18 QD19 QD20 QD21 QD22 4 SPLD TA17 GND TA2 TCE1X TPAR1 VDDT TD47 TD39 TD30 GND TD15 TD7 QD11 VDDT QD12 QD13 GND QD14 QD15 3 CPB_6 CPC_0 CPC_1 CPC_2 CPC_3 CPC_4 CPC_5 CPC_6 CPD_1 CPD_2 CPD_3 CPD_4 CPD_5 CPD_6 CPE_0 CPE_1 CPE_3 CPE_4 GND CPE_5 CPE_6 CPF_0 VDD33 CPF_1 GND MD8 MD17 MD25 MD0 MD9 MD18 GND MD1 MD10 MD19 MD26 MD33 MD42 MD51 PFRAMEX XPUHOT TA14 TA7 TWE3X TD63 TD59 TD52 TD45 TD36 TD27 TD20 TD13 TD3 QA3 QA4 QA5 QA6 QA7 QA8 9 TA13 TA6 TWE2X TD62 TD58 TD51 TD44 TD35 TD26 TD19 TD12 TD2 QDPH QARDY CPF_3 VDD33 CPF_4 CPF_5 CPF_6 MD3 MD12 MD21 MD28 MD35 MD44 MD53 MD60 MD67 MD76 MD85 MD92 MD99 MD4 MD13 MD22 GND MD36 MD45 MD54 VDD33 MD68 MD77 MD86 GND MD5 MD14 MD6 MD15 MD7 MD16 MD24 VDD33 MD23 MD29 MD37 MD46 GND MD61 MD69 MD78 MD30 MD38 MD47 MD55 MD62 MD70 MD79 MD31 VDD33 MD32 MD39 MD48 MD56 MD63 MD71 MD80 MD88 MD95 MD40 MD49 MD41 MD50 MD57 VDD33 MD58 GND MD72 MD81 MD64 MD73 MD82 MD65 MD74 MD83 MDECC7 MDECC2 VDD33 MD87 MD93 MD94 MD89 VDD33 MD90 GND MD96 MD97 MDECC6 MDECC1 MDQML MA10 GND MDECC0 MCASX MRASX MWEX MCSX 19 MBA0 GND MBA1 MDCLK NC5 18 MA9 MA8 VDD33 MA7 MA6 17 MD100 MD101 MD102 MD103 MD104 MD105 MD106 GND MD110 MD111 MD112 VDD33 MD113 GND MD119 MD120 MD107 MDECC5 MD114 MDECC4 MD121 VDD33 QNQRDY QACLKO QA0 QA1 QA2 8 VDDT QACLKI QDPL 7 MD108 MD109 JTCK JCLKBYP GND JSO4 15 JTDI JTMS 14 QDQPAR QA11 NC3 NC4 11 VDDT QA12 10 MD115 VDD33 MD116 MD117 MD118 MD122 MD123 MD124 MD125 MD126 MD127 MD128 MD129 MDECC8 MDECC3 29 28 27 26 25 24 23 22 21 20 C Pinout Diagram 29 Figure 3 Pin Locations (Bottom View) 1 AJ AH AG AF AE PAD4 PAD8 PAD13 PAD17 PAD21 PAD26 PAD31 PPAR PSERRX SPDO TA15 TA8 TA1 TA0 TCLKI TD53 TD46 TD37 TD28 TD21 TD14 TD5 QD0 QD1 QD2 QD3 QD4 QD5 2 PAD3 VDD33 3 PAD2 PAD7 4 PAD1 PAD6 PAD10 PAD15 PAD19 PAD23 PAD28 PCBEX2 5 PAD0 PAD5 PAD9 6 FRXCTL3 GND FRXCTL4 7 FIN29 FIN30 FIN31 GND 8 FIN22 FIN23 FIN24 FIN25 9 FIN15 FIN16 FIN17 FIN18 FIN19 FIN20 FIN21 PTRDYX PREQX PINTA 10 FIN10 VDDF FIN11 FIN12 GND FIN13 FIN14 VDD33 GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT TD4 QA9 GND QA10 11 FIN3 FIN4 FIN5 FIN6 FIN7 FIN8 FIN9 GND VDD GND VDD GND VDD GND VDD GND VDDT GND VDD GND VDDT GND QA13 QA14 QA15 QA16 12 13 14 15 16 17 18 19 CP8_6 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND 20 CP8_1 VDD33 CP8_2 CP8_3 GND CP8_4 CP8_5 VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 21 CP7_1 CP7_2 CP7_3 CP7_4 CP7_5 CP7_6 CP8_0 CPA_5 CPB_5 CPD_0 CPE_2 CPF_2 MD2 MD11 MD20 MD27 MD34 MD43 MD52 MD59 MD66 MD75 MD84 MD91 MD98 MD107 MD114 MD121 22 23 24 CP4_4 GND CP4_5 CP4_6 VDD33 CP5_0 CP5_1 25 CP3_4 CP3_5 CP3_6 CP4_0 CP4_1 CP4_2 CP4_3 26 CP2_4 CP2_5 CP2_6 CP3_0 CP3_1 CP3_2 CP3_3 27 CP1_5 CP1_6 CP2_0 VDD33 CP2_1 CP2_2 CP2_3 28 CP1_0 VDD33 CP1_1 CP1_2 GND CP1_3 CP1_4 CPA_0 GND CPC_0 CPD_2 CPE_4 VDD33 MD4 MD13 MD22 GND MD36 MD45 MD54 VDD33 MD68 MD77 MD86 GND MD100 MD109 VDD33 MD123 28 29 CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP9_6 CPA_6 CPB_6 CPD_1 CPE_3 CPF_3 MD3 MD12 MD21 MD28 MD35 MD44 MD53 MD60 MD67 MD76 MD85 MD92 MD99 MD108 MD115 MD122 29 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A FTXCTL5 FOUT31 FOUT24 FOUT19 FOUT12 FOUT6 FOUT0 FTXCTL6 FTXCTL0 FOUT25 FTXCLK GND FIN0 FIN1 FIN2 VDDF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 CPREF CCLK6 CCLK7 GND JSO3 JSO5 JTRSTX 12 VDDF GND FOUT13 FOUT7 FOUT1 VDDF FOUT2 GND CP6_1 CP5_2 CP6_2 CP5_3 CP6_3 CP5_4 CP6_4 GND PAD12 PAD11 PAD16 VDD33 GND PAD20 FOUT26 FOUT20 FOUT14 PAD14 FRXCTL5 PAD18 VDDF FTXCTL1 FOUT27 FOUT21 FOUT15 FOUT8 FTXCTL2 FOUT28 VDDF FRXCTL0 FIN26 FOUT16 FOUT9 FOUT3 CP6_5 CP5_5 CP6_6 CP5_6 CP7_0 CP6_0 CPA_4 GND Freescale Semiconductor, Inc... AD AC AB AA Y W V U T R P N M L K J H G F E D C B A PAD25 PAD24 PAD30 PAD29 PCBEX3 VDD33 PAD22 FRXCTL6 FRXCTL1 FIN27 PAD27 FRXCLK FRXCTL2 FIN28 GND PCLK PIRDYX PRSTX FTXCTL3 FOUT29 FOUT22 FOUT17 FOUT10 FOUT4 FTXCTL4 FOUT30 FOUT23 FOUT18 FOUT11 FOUT5 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND CCLK3 CCLK4 CCLK5 JSO2 VDDF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 CCLK0 CCLK1 CCLK2 JSO0 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND SCLK SCLKX VDD33 JSE JTCK GND JSO4 15 VDDF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 MA5 MA4 MA3 MA2 MA1 MA0 JSO1 16 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND MA11 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 PCBEX1 PCBEX0 CPA_3 CPA_2 CPA_1 VDD33 CPB_1 CPB_0 GND PPERRX PDEVSELX PSTOPX VDD33 SPDI TA16 TA9 VDDT SPLD TA17 GND TA2 SPCK TA18 TA10 TA3 TCE2X TPAR2 TD55 TD48 TD40 TD31 TD23 TD16 TD8 QD16 QD17 QD18 QD19 QD20 QD21 QD22 4 SICL TA19 TA11 TA4 TCE3X TPAR3 TD56 TD49 TD41 TD32 TD24 TD17 TD9 QD23 QD24 QD25 QD26 QD27 QD28 QD29 5 SIDA TA20 TA12 GND TWE0X TD60 TD57 VDDT TD42 TD33 TD25 GND TD10 TD0 QD30 GND QD31 QWEX GND QBCLKO 6 CPB_4 CPB_3 VDD33 CPB_2 CPC_6 CPC_5 CPC_4 CPC_3 CPE_1 CPE_0 CPD_6 CPD_5 CPF_1 VDD33 MD1 MD10 MD19 MD26 MD33 MD42 MD51 MD58 MD65 MD74 MD83 MD90 MD97 MD0 MD9 MD18 GND MD32 MD41 MD50 VDD33 MD64 MD73 MD82 VDD33 MD96 CPF_0 GND MD8 MD17 MD25 VDD33 MD40 MD49 MD57 GND MD72 MD81 MD89 GND CPE_6 CPF_6 MD7 MD16 MD24 MD31 MD39 MD48 MD56 MD63 MD71 MD80 MD88 MD95 PGNTX PIDSEL TA21 VDDT TA5 TWE1X TD61 GND TD50 TD43 TD34 VDDT TD18 TD11 TD1 VDDT CPC_2 CPC_1 CPD_4 CPD_3 CPE_5 CPF_5 MD6 MD15 MD23 MD30 MD38 MD47 MD55 MD62 MD70 MD79 MD87 MD94 GND CPF_4 MD5 MD14 VDD33 MD29 MD37 MD46 GND MD61 MD69 MD78 VDD33 MD93 XPUHOT PFRAMEX TA13 TA6 TWE2X TD62 TD58 TD51 TD44 TD35 TD26 TD19 TD12 TD2 QDPH TA14 TA7 TWE3X TD63 TD59 TD52 TD45 TD36 TD27 TD20 TD13 TD3 QA3 QA4 QA5 QA6 QA7 QA8 9 TCE0X TCE1X TPAR0 TPAR1 TD54 GND TD38 TD29 TD22 VDDT TD6 QD6 QD7 GND QD8 QD9 VDDT QD10 VDDT TD47 TD39 TD30 GND TD15 TD7 QD11 VDDT QD12 QD13 GND QD14 QD15 3 MDQM MDECC2 MDECC7 MA10 MDQML MDECC1 MDECC6 MA9 MA8 VDD33 MA7 MA6 17 MBA0 MDECC0 GND MBA1 MDCLK NC5 18 MCASX MRASX MWEX MCSX 19 GND MDECC5 MDECC4 VDD33 QBCLKI QARDY QACLKO QNQRDY VDDT QACLKI QDPL 7 QA0 QA1 QA2 8 MD106 MD105 MD104 MD103 MD113 VDD33 MD112 MD111 MD120 MD119 GND MD118 MD102 MD101 MD110 GND QA11 QDQPAR VDDT QA12 10 NC3 NC4 11 VDD33 JCLKBYP JHIGHZ JTDO 13 JTDI JTMS 14 MD117 MD116 MD125 MD124 26 27 MDECC3 MDECC8 MD129 MD128 MD127 MD126 20 21 22 23 24 25 1 2 03 30 CHAPTER 2: SIGNAL DESCRIPTIONS Pin Descriptions Grouped by Function The C-5e NP pins are categorized in groups, reflecting interfaces to the chip: Freescale Semiconductor, Inc... * * * * * * * * * * * Clock Signals CP Interface Signals Executive Processor System Interface Signals Fabric Processor Interface Signals BMU SDRAM Interface Signals TLU SRAM Interface Signals QMU SRAM (Internal Mode) Interface Signals QMU to Q-5 TMC (External Mode) Interface Signals Power Supply Signals Test Signals No Connection Pins Pins conform to Joint Electronic Devices Engineering Council (JEDEC) standards. LVTTL and LVPECL Specifications C-5e NP pins are the following types: * * Low Voltage TTL-Compatible (LVTTL). The C-5e NP's LVTTL pins conform to the JEDEC JESD8-B specification. Low Voltage Positive Emitter Coupled Logic (LVPECL). All of the signals in the following tables in this chapter denote whether the individual signal is an Input (I), Output (O), both Input and Output (I/O), or power (P). In addition, a PU, PD, and nc are used. The PU indicates that an internal resistor will pullup the pad if left unconnected. PD indicates an internal pulldown resistor. NC means the pad is to be left unconnected. C Pin Descriptions Grouped by Function 31 Clock Signals Table 6 describes the C-5e NP clock signals. Table 6 Clock and Reference Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION SCLK* SCLKX* G15 F15 G14 F14 E14 G13 F13 E13 F12 E12 G12 1 1 1 1 1 1 1 1 1 1 1 11 LVPECL LVPECL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVPECL I I IPD IPD IPD IPD IPD IPD IPD IPD IPD Core Clock Rate (Differential) 1_544MHZ_CLK (T1) 2_048MHZ_CLK (E1) 34_368MHZ_CLK (E3) 44_736MHZ_CLK (T3) 50MHZ_CLK (100Mbit Ethernet) 106_25MHZ_CLK (Fibre Channel) 125MHZ_CLK (Gigabit Ethernet) 155_52MHZ_CLK (OC-3) Reference Freescale Semiconductor, Inc... CCLK0 CCLK1 CCLK2 CCLK3 CCLK4 CCLK5 CCLK6 CCLK7 CPREF TOTAL * SCLK and SCLKX must not be AC-coupled. The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5e NP. It is also possible to use one or more CCLKn inputs for other frequencies. Contact your Motorola representative for more information. If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must be wired to an external reference, as specified in Table 38 on page 75. If none of the CPs are configured for LVPECL operation, then the CPREF pin can be left unconnected. 03 32 CHAPTER 2: SIGNAL DESCRIPTIONS CP Interface Signals The C-5e NP's 16 CPs support various network physical interfaces, providing a serial interface to the PHY layer. Interfaces are configured via bits in the C-5e NP register set. Many interfaces are possible by programming the configuration registers. CPs can be used individually or in a cluster (four CPs) to implement the various interfaces. Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven physical I/O pins associated with each CP. All pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can be configured as differential pairs for LVPECL compatibility. In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for receive and four for transmit) or four CPs that share the transmit and receive functions for non-wire speed applications. During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the SDPs, with each getting access to the necessary I/O pins. The signals for the following CP physical interfaces are included in this section: Freescale Semiconductor, Inc... * * * * * * DS1/T1 Framer Interface Configuration 10/100 Ethernet (RMII) Configuration Gigabit Ethernet (GMII) Configuration Gigabit Ethernet and Fibre Channel TBI Configuration SONET OC-3 Transceiver Interface Configuration SONET OC-12 Transceiver Interface Configuration C Pin Descriptions Grouped by Function 33 Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters) CP CLUSTER 1 SIGNAL PIN # CP CLUSTER 2 SIGNAL PIN # CP CLUSTER 3 SIGNAL PIN # CP CLUSTER 4 SIGNAL PIN # CP0_0 CP0_1 AJ29 AH29 AG29 AF29 AE29 AD29 AC29 AJ28 AG28 AF28 AD28 AC28 AJ27 AH27 AG27 AE27 AD27 AC27 AJ26 AH26 AG26 AF26 AE26 AD26 AC26 AJ25 AH25 AG25 CP4_0 CP4_1 CP4_2 CP4_3 CP4_4 CP4_5 CP4_6 CP5_0 CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 CP6_0 CP6_1 CP6_2 CP6_3 CP6_4 CP6_5 CP6_6 CP7_0 CP7_1 CP7_2 CP7_3 CP7_4 CP7_5 CP7_6 AF25 AE25 AD25 AC25 AJ24 AG24 AF24 AD24 AC24 AJ23 AH23 AG23 AE23 AD23 AC23 AJ22 AH22 AG22 AF22 AE22 AD22 AC22 AJ21 AH21 AG21 AF21 AE21 AD21 CP8_0 CP8_1 CP8_2 CP8_3 CP8_4 CP8_5 CP8_6 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 CP9_6 CPA_0 CPA_1 CPA_2 CPA_3 CPA_4 CPA_5 CPA_6 CPB_0 CPB_1 CPB_2 CPB_3 CPB_4 CPB_5 CPB_6 AC21 AJ20 AG20 AF20 AD20 AC20 AJ19 AH19 AG19 AF19 AE19 AD19 AC19 AB29 AB28 AB26 AB25 AB24 AB22 AB21 AA29 AA27 AA26 AA25 AA23 AA22 AA21 Y29 CPC_0 CPC_1 CPC_2 CPC_3 CPC_4 CPC_5 CPC_6 CPD_0 CPD_1 CPD_2 CPD_3 CPD_4 CPD_5 CPD_6 CPE_0 CPE_1 CPE_2 CPE_3 CPE_4 CPE_5 CPE_6 CPF_0 CPF_1 CPF_2 CPF_3 CPF_4 CPF_5 CPF_6 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21 W29 W28 W27 W26 W25 W24 W23 W22 W21 V29 V28 V26 V25 V24 V22 V21 U29 U27 U26 U25 Freescale Semiconductor, Inc... CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP1_0 CP1_1 CP1_2 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 CP2_2 CP2_3 CP2_4 CP2_5 CP2_6 CP3_0 CP3_1 CP3_2 CP3_3 CP3_4 CP3_5 CP3_6 03 34 CHAPTER 2: SIGNAL DESCRIPTIONS DS1/T1 Framer Interface Configuration Table 8 describes the serial framer interface signals. For each CP (0-15), you can implement one serial Framer interface. Table 8 DS1/T1 Framer Interface Signals SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION Freescale Semiconductor, Inc... CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 TOTAL PINS * Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 1 1 1 1 1 1 1 7 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc OPD IPU OPD OPU IPD IPU ncPU TCLK RCLK TData TFrame RData RFrame nc Transmit Clock (1.544MHz) Receive Clock (1.544MHz) Transmit Data Transmit Frame Synchronization Receive Data Receive Frame Synchronization nc n can be from 0 to 15. See Table 7. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. 10/100 Ethernet (RMII) Configuration Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface (RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface. Table 9 10/100 Ethernet Signals SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 CPn_1 Table 7 Table 7 1 1 LVTTL LVTTL OPD IPU REF_CLK CRS_DV CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 TOTAL PINS * Table 7 Table 7 Table 7 Table 7 Table 7 1 1 1 1 1 7 LVTTL LVTTL LVTTL LVTTL LVTTL OPD OPU IPD IPU OPU TXD(0) TXD(1) RXD(0) RXD(1) TX_EN Transmit and Receive Clock (50MHz) Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... RX_DV indicates that a receive frame is in progress and the data present on the RXD pins is valid. It is asserted if this signal is a 1 for more than one cycle. Transmit Data 0 (first on wire) Transmit Data 1 (second on wire) Receive Data 0 (first on wire) Receive Data 1 (second on wire) Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable. n can be from 0 to 15. See Table 7. C Pin Descriptions Grouped by Function 35 Gigabit Ethernet (GMII) Configuration Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways: * * Use one CP cluster when density is more important than wire-speed performance because you can then implement up to four Gigabit Ethernet ports per C-5e NP. Use two CP clusters for wire-speed performance and additional processing power. You can implement up to two Gigabit Ethernet ports per C-5e NP. Freescale Semiconductor, Inc... Table 10 lists the possible CP cluster combinations you can use and Figure 4 shows receive and transmit pin configurations by cluster. Table 11 lists the signals and pinouts for Gigabit Ethernet (GMII). Table 10 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel CLUSTER SINGLE CLUSTER MODE (TBI OR GMII) TWO CLUSTER MODE (GMII)* 0 1 2 3 * Port 1 Tx and Rx Port 2 Tx and Rx Port 3 Tx and Rx Port 4 Tx and Rx Port 1 Tx Port 1 Rx Port 2 Tx Port 2 Rx The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits. 03 36 CHAPTER 2: SIGNAL DESCRIPTIONS Figure 4 GMII/TBI Transmit and Receive Pin Configurations Single Cluster Mode Pin Configuration Tx Two Cluster Mode Pin Configuration Cluster 0 Rx Tx } Port 1 } Port 2 } Port 3 } Port 4 Tx Cluster 0 Rx nc Freescale Semiconductor, Inc... Tx Cluster 1 Rx Tx Cluster 1 nc Rx Tx Cluster 2 Cluster 3 Rx Tx Rx Cluster 2 Cluster 3 nc = not connected Rx nc Tx nc Rx } } Port 1 Port 2 Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL OPD IPU OPD OPU OPD OPU OPU T_CLK TCLKI TXD(0) TXD(1) TXD(2) TXD(3) TX_EN GMII Transmit Clock (125MHz). This clock is used to synchronize the transmit data. MII transmit clock. Transmit data aligned to this clock input from phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable. C Pin Descriptions Grouped by Function 37 Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued) SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn+1_0 CPn+1_1 CPn+1_2 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL ncPD nc IPU OPD OPU OPD OPU OPU COL TXD(4) TXD(5) TXD(6) TXD(7) TX_ER nc Collision. Asserted when both RX_DV and TX_EN are valid during half duplex operation. Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide receive data, most significant bit) Transmit Error. Asserting TX_ER when TX_EN is a 1 causes transmission of the designated "bad code" in lieu of the normal encoded data on the twisted pair data. nc Receive Clock (125MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Receive Data Valid. Indicates that there is a receive frame in progress and that the data present on the RXD signals is valid. nc Carrier Sense. Indicates traffic is on the link. CRS is asserted when a non-idle condition is detected on the receive data stream. CRS is deasserted when an end of frame or idle condition is detected. Receive Data Receive Data Receive Data Receive Data (most significant bit) Receive Error Detected. Indicates that there has been an error received in the receive frame. Freescale Semiconductor, Inc... CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL ncPD nc IPU IPD IPU IPD IPU IPU RCLK RXD(0) RXD(1) RXD(2) RXD(3) RX_DV ncPD nc IPU CRS CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6 TOTAL PINS * Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 28 LVTTL LVTTL LVTTL LVTTL LVTTL IPD IPU IPD IPU IPU RXD(4) RXD(5) RXD(6) RXD(7) RX_ER n can be 0, 4, 8, or 12. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. 03 38 CHAPTER 2: SIGNAL DESCRIPTIONS Gigabit Ethernet and Fibre Channel TBI Configuration 1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same way as Gigabit Ethernet (GMII). Table 10 shows the possible CP pin combinations you can use and Figure 4 shows receive and transmit pin configurations by cluster. Table 12 shows the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI. The unused pins for the two cluster configurations should be wired down using a resistor. Freescale Semiconductor, Inc... Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL OPD ncPU OPD OPU OPD OPU OPU ncPD ncPU OPD OPU OPD OPU OPU ncPD IPU IPD IPU IPD IPU IPU TCLK nc TXD(9) TXD(8) TXD(7) TXD(6) TXD(1) nc nc TXD(5) TXD(4) TXD(3) TXD(2) TXD(0) nc RCLK RXD(9) RXD(8) RXD(7) RXD(6) RXD(1) Transmit Clock (125MHz). This clock is used to synchronize the transmit data. nc Transmit Data (ten bits wide, last on wire) Transmit Data Transmit Data Transmit Data Transmit Data nc nc Transmit Data Transmit Data Transmit Data Transmit Data Transmit Data (ten bits wide, first on wire) nc Receive Clock (62.5 MHz) Receive Data (ten bits wide, last on wire) Receive Data Receive Data Receive Data Receive Data C Pin Descriptions Grouped by Function 39 Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued) SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn+3_0 CPn+3_1 CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6 TOTAL PINS * Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 28 nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL ncPD IPU IPD IPU IPD IPU IPU nc RCLKN RXD(5) RXD(4) RXD(3) RXD(2) RXD(0) nc Receive Clock Inverted Receive Data Receive Data Receive Data Receive Data Receive Data (ten bits wide, first on wire) Freescale Semiconductor, Inc... n can be 0, 4, 8, or 12 Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. SONET OC-3 Transceiver Interface Configuration Table 13 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each CP (0-15), you can implement a single OC-3 interface. Table 13 OC-3 Signals SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 TOTAL PINS * Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 1 1 1 1 1 1 1 7 LVPECL IPD LVPECL IPU LVPECL OPD LVPECL IPU LVPECL IPD LVPECL IPU LVPECL IPU RCLK_H RCLK_L TXD_H TXD_L RXD_H RXD_L SIGNAL_DET Receive Clock noninverted side of pair (155.52MHz) Receive Clock inverted side of pair (155.52MHz) Transmit Data noninverted side of pair Transmit Data inverted side of pair Receive Data noninverted side of pair Receive Data inverted side of pair A light level above a certain threshold is present at the optical receiver - single ended LVPECL. n can be from 0 to 15. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring. 03 40 CHAPTER 2: SIGNAL DESCRIPTIONS SONET OC-12 Transceiver Interface Configuration SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a CP within a cluster spends half its time performing receive functions, and the other half performing transmit functions. Table 14 shows a CP Cluster configured for one OC-12 interface. Table 14 OC-12 Signals Example Freescale Semiconductor, Inc... SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL OPD IPU OPD OPU OPD OPU OPU ncPD ncPU OPD OPU OPD OPU ncPU ncPD IPU IPD IPU IPD IPU IPU TCLK TCLKI TXD(0) TXD(1) TXD(2) TXD(3) 00F nc nc TXD(4) TXD(5) TXD(6) TXD(7) nc nc RCLK RXD(0) RXD(1) RXD(2) RXD(3) FP Deskewed Transmit Clock (77.76MHz). This clock is used to synchronize the transmit data. Transceiver Transmit Clock. This clock sets the frequency of the transmit data and is typically sourced by the PHY chip. Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Out of Frame nc nc Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide data, most significant bit) nc nc Receive Clock (77.76MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Frame Synchronization Pulse. This is valid during the third A2 of the receive SONET frame. C Pin Descriptions Grouped by Function 41 Table 14 OC-12 Signals Example (continued) SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION CPn+3_0 CPn+3_1 CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6 TOTAL PINS * Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 1 1 1 1 1 1 1 28 nc nc LVTTL LVTTL LVTTL LVTTL nc ncPD ncPU IPD IPU IPD IPU ncPU nc nc RXD(4) RXD(5) RXD(6) RXD(7) nc nc nc Receive Data Receive Data Receive Data Receive Data (most significant bit) nc Freescale Semiconductor, Inc... n can be 0, 4, 8, or 12 Reference Table 7 for pin numbers for a different cluster. 03 42 CHAPTER 2: SIGNAL DESCRIPTIONS Executive Processor System Interface Signals The XP's system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. It is also the primary interface used for initializing the C-5e NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM interface signals. PCI Signals The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or 66MHz. The PCI is fully compliant with PCI Specification revision 2.1. Table 15 describes the PCI signals. Freescale Semiconductor, Inc... Table 15 PCI Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION PAD0 - PAD31 AJ5, AJ4, AJ3, AJ2, AJ1, AH5, AH4, 32 AH3, AH1, AG5, AG4, AG3, AG2, AG1, AF5, AF4, AF2, AF1, AE5, AE4, AE3, AE1, AD5, AD4, AD3, AD2, AD1, AC5, AC4, AC3, AC2, AC1 AB6, AB5, AB4, AB2 4 PCI I/O Multiplexed Address/Data Bus. These signals are multiplexed address and data bits. The C-5e NP receives addresses as target and drives addresses as master. It drives the data and receives read data as master. Command byte enables. These signals are multiplexed command and byte enabled signals. The C-5e NP receives byte enables as target and drives byte enables as master. Parity. This signal carries even parity for AD and CBE# pins. It has the same receive and drive characteristics as the address and data bus, except that it is one PCI cycle later. Cycle frame Target ready for data transfer Initiator ready for data transfer Target transaction stop request Target device selected Bus parity error System error Bus clock Bus reset Initiator bus request (arbitration) PCBEX0 - PCBEX3 PCI I/O PPAR AB1 1 PCI I/O PFRAMEX PTRDYX PIRDYX PSTOPX PDEVSELX PPERRX PSERRX PCLK PRSTX PREQX W9 AB9 AB8 AA5 AA4 AA3 AA1 AA7 AA8 AA9 1 1 1 1 1 1 1 1 1 1 PCI PCI PCI PCI PCI PCI PCI IPD PCI PCI I/O I/O I/O I/O I/O I/O I/O I I O C Pin Descriptions Grouped by Function 43 Table 15 PCI Signals (continued) SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION PGNTX PIDSEL PINTA TOTAL PINS Y7 Y8 Y9 1 1 1 50 IPD PCI PCI I I O Initiator bus grant (arbitration) Initialization device select Interrupt Freescale Semiconductor, Inc... Serial Interface Signals The Serial interface is a bidirectional two-wire serial bus. It can use one of the following formats: * * An 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). A 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports transfers up to 25MHz (high speed). The signals and pins are identical for both the high and low speed protocols. Which of the two data rates used is selected by the state of the PROM interface's SPLD signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is selected. The bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism. Table 16 Serial Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION SICL SIDA TOTAL PINS Y5 Y6 1 1 2 LVTTL LVTTL IPD/O Serial Clock line IPD/O Serial Data line 03 44 CHAPTER 2: SIGNAL DESCRIPTIONS PROM Interface Signals The PROM interface is a low speed I/O port that allows the C-5e NP to communicate through external logic to PROM. The PROM clock is 1/2 to 1/16 the core clock rate. The maximum PROM size addressable is 4MBytes, and must use a "by 16" part. The PROM signals are listed in Table 17. Table 17 PROM Interface Signals Freescale Semiconductor, Inc... SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION SPDO SPDI SPLD Y1 Y2 Y3 1 1 1 LVTTL LVTTL LVTTL O IPD O Serial Data Out Serial Data In When load is asserted on a positive clock edge, the external logic performs a parallel load. On each positive clock edge when load is de-asserted, the shift registers shift. When the PROM interface is idle: * If SPLD is asserted HI it indicates low speed serial protocol, * SPCK TOTAL PINS If asserted LOW it indicates MDIO serial protocol. Y4 1 4 LVTTL O Clock Figure 5 shows the connections between the PROM Interface and external board logic. The application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. Both devices should be positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When SPLD is deasserted the shift register shifts. C Pin Descriptions Grouped by Function 45 Figure 5 PROM Interface Diagram 21 C-5e Network Processor 0 PROM_ADDR<21:1> 21 CE External Logic SPDO 21 6 1 0 SPDI 21 60 Freescale Semiconductor, Inc... 15 31 16 PROM _H_Word PROM _Return_Data 15 Internal Shift Register 21 0 External Shift Register 0 CE PROM_ADDR<21:1> PROM _LO_Word 21 PROM Clock Gen. SPCLK PROM Sequencer SPLD PROM PROM_Data 1 16 The PROM interface operates in the following manner (Note that two accesses are piplined together to execute one 32-bit fetch). The steps are shown in Figure 6. 1 The PROM_ADDR is loaded into the network processor internal shift register. 2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles. 3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register. 4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift register. 5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register and the first PROM_DATA into the external shift register. 6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network processor internal shift register. 7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network processor PROM_RETURN_DATA register and the second PROM_DATA into the external shift register. 03 46 CHAPTER 2: SIGNAL DESCRIPTIONS 8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the network processor internal shift register. 9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the network processor PROM_RETURN_DATA register. Figure 6 PROM Interface Timing Outline Freescale Semiconductor, Inc... XP PROM Interface outline SPLD SPDTO Q< Q< Q< Q< A5 A1 A2 A3 A4 SPDTI XP PROM Interface detail 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 D1 D2 D3 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 SPCLK SPLD SPDTO x A1 AAAAAAAAAAAA 20 19 18 17 16 15 14 13 12 11 10 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A CE 0 A2 A3 A4 1 2 The PROM_ADDR is loaded into the C-5's internal shift register. The PROM_ADDR is shifted into the external shift register. (SPCLK Rising Edge used for shifting) 3 5 4 The PROM_DATA is loaded into the external shift register. D1 x DDDDDDD 15 14 13 12 11 10 9 D 8 D 7 D 6 D 5 DD 43 D 2 D 1 D 0 x x x x x x The PROM_ADDR is loaded into the external presentation register. The PROM_DATA is presenting. D2 SPDTI 6 8 7 The PROM_DATA is shifted into the C-5's Internal shift register. 9 The PROM_DATA is loaded into the C-5's internal PROM_RETURN_DATA register. C Pin Descriptions Grouped by Function 47 General System Interface Signal Table 18 provides the signal for the Executive Processor reset power status and I/O clock. The C-5e NP can be powered up with the XP either running or with the XP in reset mode similar to the CPs. When the XP remains in reset mode, an external host can be used to control the initialization of the C-5e NP. Table 18 General System Interface Signal Freescale Semiconductor, Inc... SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION XPUHOT W8 1 LVTTL IPD Sample at Power On Reset determines if the XP RISC Core is held in reset. Low equals reset and High equals active. During normal operation, this is an external interrupt. TOTAL PINS 1 03 48 CHAPTER 2: SIGNAL DESCRIPTIONS Fabric Processor Interface Signals The FP has logical signal interfaces: a receive data interface and a transmit data interface, each with its own control, data, and clock signals. The interface has the following characteristic: The interface clocks FRXCLK and FTXCLK can have a different frequency from the core C-5e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to 125MHz. Freescale Semiconductor, Inc... FRXCLK and FTXCLK can be independent of each other; typically they have the same frequency, but are allowed to be skewed relative to each other. Each data bus can be configured for widths of 8 (data bits 7:0 are used), 16 (bits 15:0), or 32 (bits 31:0). In 8bit mode, data bits 31:8 are unused. In 16bit mode, data bits 31:16 are unused. Table 19 Fabric Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION FIN0 - FIN31 AE12, AD12, AC12, AJ11, AH11, AG11,AF11, AE11, AD11, AC11, AJ10, AG10, AF10, AD10, AC10, AJ9, AH9, AG9, AF9, AE9, AD9, AC9, AJ8, AH8, AG8, AF8, AE8, AD8, AC8, AJ7, AH7, AG7 AJ18, AH18, AG18, AE18, AD18, AC18, AJ17, AH17, AF17, AE17, AD17, AC17, AJ16, AH16, AG16, AF16, AE16, AD16, AC16, AJ15, AG15, AF15, AD15, AC15, AJ14, AH14, AG14, AF14, AE14, AD14, AC14, AJ13 AC6 AG12 AE7, AD7, AC7, AJ6, AG6, AF6, AD6 AH13, AF13, AE13, AD13, AC13, AJ12, AH12 32 LVTTL IPD Fabric Data Bus In FOUT0 - FOUT31 32 LVTTL O Fabric Data Bus Out FRXCLK FTXCLK FRXCTL0 - FRXCTL6 FTXCTL0 - FTXCTL6 TOTAL PINS 1 1 7 7 80 LVTTL LVTTL LVTTL LVTTL IPD IPD Receive Clock Transmit Clock IPD, O Receive Control Signals IPD, O Transmit Control Signals The following tables list the Fabric Interface pin mappings: * * * Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 20 Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 21 PRIZMA Mode mappings are listed in Table 22 (PRIZMA protocol is a subset of Utopia3 PHY) C Pin Descriptions Grouped by Function 49 * * RECEIVE SIGNALS Power X(CSIX-L0) Mode mappings are listed in Table 23 CSIX-L1 Mode mappings are listed in Table 24 Table 20 Utopia1*, 2*, 3 ATM Mode, C-5e Network Processor to Fabric Interface Pin Mapping TRANSMIT SIGNALS I/O UTOPIA NOTE C-5E NETWORK PROCESSOR I/O UTOPIA NOTE Freescale Semiconductor, Inc... C-5E NETWORK PROCESSOR FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6 * Output Input Input Input Input Input Input RxEnb* RxClav RxSOC n/a n/a n/a RxPrty Pullup or No Connection FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6 Output Input Output Input Input Input Output TxEnb* TxClav TxSOC n/a n/a n/a TxPrty Pullup or No Connection Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low. Table 21 Utopia1*, 2*, 3 PHY Mode, C-5e Network Processor to Fabric Interface Pin Mapping RECEIVE SIGNALS C-5E NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-5E NETWORK PROCESSOR I/O UTOPIA NOTE FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6 * Input Output Input Input Input Input Input TxEnb* TxClav TxSOC n/a n/a n/a TxPrty Pullup No Connection FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6 Input Output Output Input Input Input Output RxEnb* RxClav RxSOC n/a n/a n/a RxPrty Pullup No Connection Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low. When configuring two C-5e network processors back-to-back using the Fabric Port, set up the transmit side of each C-5e network processor in Utopia ATM mode and the receive side of each C-5e network processor in Utopia PHY mode. 03 50 CHAPTER 2: SIGNAL DESCRIPTIONS Table 22 PRIZMA Mode, C-5e Network Processor to Fabric Interface Pin Mapping RECEIVE SIGNALS C-5E NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-5E NETWORK PROCESSOR I/O UTOPIA NOTE FRXCTL0 Input Output Input Input Input Input Input TxEnb* TxClav TxSOP n/a n/a n/a TxPrty Not connected to fabric. No connection FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 Input Output Output Input Input Input Output RxEnb* RxClav RxSOP n/a n/a n/a RxPrty Not connected to fabric. No Connection Freescale Semiconductor, Inc... FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6 * Optional FTXCTL6 Optional Both TxEnb and RxEnb are Active Low. Table 23 Power X(CSIX-L0) Mode, C-5e Network Processor to Fabric Interface Pin Mapping RECEIVE SIGNALS C-5E NETWORK PROCESSOR I/O POWER X NOTE TRANSMIT SIGNALS C-5E NETWORK PROCESSOR I/O POWER X NOTE FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6 Input Input Input Input Input Input Input RxCtrl[0] RxCtrl[1] RxCtrl[2] RxPrty[3] RxPrty[2] RxPrty[1] RxPrty[0] FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6 Output Output Output Output Output Output Output TxCtrl[0] TxCtrl[1] TxCtrl[2] TxPrty[3] TxPrty[2] TxPrty[1] TxPrty[0] For the CSIX-L1 Mode, VDDF= 2.5V. C Pin Descriptions Grouped by Function 51 Table 24 CSIX-L1 Mode, C-5e Network to Fabric Interface Pin Mapping FPRX SIGNALS C-5E NP I/O CSIX-L1 NOTE FPTX SIGNALS C-5E NP I/O CSIX-L1 NOTE FRxCTL0 FRxCTL1 FRxCTL2 FRxCTL3 FRxCTL4 FRxCTL5 FRxCTL6 Input Input Input Input Input Input Input n/a n/a TxSOF n/a n/a n/a TxPrty FTxCTL0 FTxCTL1 FTxCTL2 FTxCTL3 FTxCTL4 FTxCTL5 FTxCTL6 Input Input Output Input Input Input Output n/a n/a RxSOF n/a n/a n/a RxPrty Freescale Semiconductor, Inc... 03 52 CHAPTER 2: SIGNAL DESCRIPTIONS BMU SDRAM Interface Signals The BMU and SDRAM interface signals are described in Table 25. The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines and all 12 address lines must be connected to the SDRAM in order for the BMU to be able to read and write external SDRAM properly. Table 25 BMU SDRAM Interface Signals Freescale Semiconductor, Inc... SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION MD0 - MD129 U23, U22, U21, T29, T28, T27, T26, 130 T25, T24, T23, T22, T21, R29, R28, R27, R26, R25, R24, R23, R22, R21, P29, P28, P26, P25, P24, P22, P21, N29, N27, N26, N25, N23, N22, N21, M29, M28, M27, M26, M25, M24, M23, M22, M21, L29, L28, L27, L26, L25, L24, L23, L22, L21, K29, K28, K26, K25, K24, K22, K21, J29, J27, J26, J25, J23, J22, J21, H29, H28, H27, H26, H25, H24, H23, H22, H21, G29, G28, G27, G26, G25, G24, G23, G22, G21, F29, F28, F26, F25, F24, F22, F21, E29, E27, E26, E25, E23, E22, E21, D29, D28, D27, D26, D25, D24, D23, D22, D21, C29, C28, C26, C25, C24, C22, C21, B29, B27, B26, B25, B23, B22, B21, A29, A28, A27, A26, A25, A24, A23, A22 9 12 LVTTL IPD/O Data Lines In MDECC0 - MDECC8 E19, F19, G19, A20, C20, D20, F20, G20, A21 MA0 - MA11 B16, C16, D16, E16, F16, G16, A17, B17, D17, E17, F17, G17 LVTTL LVTTL IPD/O Stored as data, ECC bits OPD Address Outputs: A0-A11 are sampled during the ACTIVE command and READ/WRITE to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a LOAD MODE REGISTER command Bank Address Outputs: BA0 and BA1 define which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. NOTE: MCSX is considered part of the command code. MBA0 - MBA1 E18, C18 2 LVTTL OPD MCASX D19 1 LVTTL OPD C Pin Descriptions Grouped by Function 53 Table 25 BMU SDRAM Interface Signals (continued) SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION MRASX C19 1 LVTTL OPD Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Chip Select: MCSX enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when MCSX is registered HIGH. MCSX provides the external bank selection on systems with multiple banks. MCSX is considered part of the command code. Input/Output Mask: MDQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when MDQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a high Z state (two-clock latency) when MDQM is sampled HIGH during the READ cycle. NOTE: MDQML is an identical copy of MDQM used to drive the loading on SDRAM configurations with 2 DQM pins. Clock: MDCLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of the MDCLK. MDCLK also increments the internal burst counter and controls the output registers. MWEX B19 1 LVTTL OPD Freescale Semiconductor, Inc... MCSX A19 1 LVTTL OPD MDQM MDQML G18 F18 1 1 LVTTL LVTTL OPD OPD MDCLK B18 1 LVTTL IPD TOTAL PINS 160 03 54 CHAPTER 2: SIGNAL DESCRIPTIONS TLU SRAM Interface Signals The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 133MHz using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to 64Mbits. The TLU SRAM interface signals are described in Table 26. Table 26 TLU SRAM Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION Freescale Semiconductor, Inc... TD0 - TD63 G6, G7, G8, G9, G10, H1, H2, H3, H4, H5, H6, H7, H8, 64 H9, J1, J3, J4, J5, J7, J8, J9, K1, K2, K4, K5, K6, K8, K9, L1, L2, L3, L4, L5, L6, L7, L8, L9, M1, M2, M3, M4, M5, M6, M7, M8, M9, N1, N3, N4, N5, N7, N8, N9, P1, P2, P4, P5, P6, P8, P9, R6, R7, R8, R9 T1, U1, U3, U4, U5, U7, U8, U9, V1, V2, V4, V5, V6, V8, V9, W1, W2, W3, W4, W5, W6, W7 R2, R3, R4, R5 T2, T3, T4, T5 T6, T7, T8, T9 R1 22 4 4 4 1 99 LVTTL IPD/O TLU Memory Data TA0 - TA21 TPAR0 - TPAR3 TCE0X - TCE3X TWE0X - TWE3X TCLKI TOTAL PINS LVTTL LVTTL LVTTL LVTTL LVTTL OPD TLU Memory Address IPD/O Word Data Parity (i.e. TPAR0 across TD15:0) OPD OPD IPD TLU Memory Chip Enable TLU Memory Write Enable TLU Clock Input C Pin Descriptions Grouped by Function 55 QMU SRAM (Internal Mode) Interface Signals The QMU signals are described in Table 27. Table 27 QMU SRAM (Internal Mode) Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION QA0 - QA16 Freescale Semiconductor, Inc... C8, B8, A8, F9, E9, D9, C9, B9, A9, F10, D10, C10, A10, G11, F11, E11, D11 G1, F1, E1, D1, C1, B1, G2, F2, D2, C2, A2, G3, E3, D3, B3, A3, G4, F4, E4, D4, C4, B4, A4, G5, F5, E5, D5, C5, B5, A5, F6, D6 C11 E8 D8 C6 A6 E7 D7 B7 A7 F8 17 32 LVTTL LVTTL O Address [16:0] QD0 - QD31 IPD/O Data QDQPAR QARDY QNQRDY QWEX QBCLKO QBCLKI QACLKO QACLKI QDPL QDPH TOTAL PINS 1 1 1 1 1 1 1 1 1 1 59 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL IPD IPD IPD O O IPD O IPD nc nc nc Write Enable nc nc nc Input Clock IPD/O Data Parity Low IPD/O Data Parity High 03 56 CHAPTER 2: SIGNAL DESCRIPTIONS QMU to Q-5 TMC (External Mode) Interface Signals The QMU to Q-5 Traffic Management Coprocessor (TMC) signals are described in Table 28. Table 28 QMU to Q-5 (External Mode) Interface Signals SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION QA0 - QA15 Freescale Semiconductor, Inc... C8, B8, A8, F9, E9, D9, C9, B9, A9, F10, D10, C10, A10, G11, F11, E11 D11 G1, F1, E1, D1, C1, B1, G2, F2, D2, C2, A2, G3, E3, D3, B3, A3, G4, F4, E4, D4, C4, B4, A4, G5 F5, E5, D5, C5, B5, A5, F6, D6 C11 E8 D8 C6 A6 E7 D7 B7 A7 F8 16 1 24 8 1 1 1 1 1 1 1 1 1 1 59 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL O O IPD IPD IPD IPD IPD O O IPD O IPD O O Enqueue Data [8:23] Enqueue Parity Dequeue Data [0:23] Enqueue Data [0:7] Dequeue Parity Dequeue Ack Ready Enqueue Ready Dequeue Ready Output ClockB Input ClockB Output ClockA Input ClockA Dequeue Ack [0] Dequeue Ack [1] QA16 QD0 - QD23 QD24 - QD31 QDQPAR QARDY QNQRDY QWEX QBCLKO QBCLKI QACLKO QACLKI QDPL QDPH TOTAL PINS C Pin Descriptions Grouped by Function 57 Power Supply Signals Table 29 Power Supply Signals SIGNAL NAME PIN # Power supply, and ground signals are described in Table 29. TOTAL TYPE SIGNAL DESCRIPTION VDD Freescale Semiconductor, Inc... J13, J15, J17, J19, K12, K14, K16, K18, L11, L13, L15, 57 L17, L19, M12, M14, M16, M18, N13, N15, N17, N19, P12, P14, P16, P18, R11, R13, R15, R17, R19, T12, T14, T16, T18, U11, U13, U15, U17, U19, V12, V14, V16, V18, W11, W13, W15, W17, W19, Y12, Y14, Y16, Y18, AA11, AA13, AA15, AA17, AA19, B20, B28, C13, C17, C23, E15, F23, F27, H12, H14, H16, H18, H20, J28, K20, K23, M20, N24, P20, P27, T20, U28, V20, V23, Y20, AA6, AA24, AB3, AB10, AB18, AB20, AB27, AE24, AF3, AF27, AH2, AH20, AH28 38 P Core Supply Voltage (1.2V Input) VDD33 P I/O Supply Voltage (3.3V Input) GND B6, B15, B24, C3, C27, D12, D18, E2, E6, E10, E20, E24, 122 E28, H11, H13, H15, H17, H19, J6, J10, J12, J14, J16, J18, J20, J24, K3, K11, K13, K15, K17, K19, K27, L10, L12, L14, L16, L18, L20, M11, M13, M15, M17, M19, N2, N10, N12, N14, N16, N18, N20, N28, P7, P11, P13, P15, P17, P19, P23, R10, R12, R14, R16, R18, R20, T11, T13, T15, T17, T19, U6, U10, U12, U14, U16, U18, U20, U24, V3, V11, V13, V15, V17, V19, V27, W10, W12, W14, W16, W18, W20, Y11, Y13, Y15, Y17, Y19, AA2, AA10, AA12, AA14, AA16, AA18, AA20, AA28, AB7, AB11, AB13, AB15, AB17, AB19, AB23, AE2, AE10, AE20, AE28, AF7, AF12, AF18, AF23, AH6, AH15, AH24 AB12, AB14, AB16, AE6, AE15, AG13, AG17, AH10 B2, B10, C7, F3, F7, H10, J2, J11, K7, K10, M10, N6, N11, P3, P10, T10, U2, V7, V10, Y10 8 20 245 P Ground VDDF VDDT TOTAL PINS P P Fabric I/O supply (3.3 or 2.5V) TLU and QMU I/O supply (3.3V) 03 58 CHAPTER 2: SIGNAL DESCRIPTIONS Test Signals Test signals are described in Table 30. Table 30 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION JTCK JTMS C15 A14 1 1 LVTTL LVTTL IPD IPD Test Clock Test Mode Select. High selects modes as defined in the IEEE 1149.1 JTAG specification. Test Reset (low active) Test Data In Test Data Out Turns off all output drivers when High 1X or 2X Clock Mode Select. Low selects 1X, High selects 2X. Scan Enable. High enables scan test. Scan Out Pins Freescale Semiconductor, Inc... JTRSTX JTDI JTDO JHIGHZ JCLKBYP JSE JS00-JS05 TOTAL PINS A12 B14 A13 B13 C14 D15 D14, A16, D13, C12, A15, B12 1 1 1 1 1 1 6 14 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL IPD IPD O IPD IPD IPD O During JTAG, SCLK and SCLKX must remain as differential inputs. No Connection Pins Table 31 No Connection Pins SIGNAL NAME PIN # No connection pins are listed in Table 31. TOTAL TYPE I/O SIGNAL DESCRIPTION NC3 - NC5 TOTAL PINS B11, A11, A18 3 3 nc IPD/O Reserved for future functionality C Signals Grouped by Pin Number 59 Signals Grouped by Pin Number The C-5e NP signals are listed by pin number in Table 32. Table 32 Signals Listed by Pin Number PIN FUNCTION PIN FUNCTION PIN A 1-29 FUNCTION PIN FUNCTION Freescale Semiconductor, Inc... A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6 C7 C8 Not present QD10 QD15 QD22 QD29 QBCLKO QDPL QA2 QD5 VDDT QD14 QD21 QD28 GND QACLKI QA1 QD4 QD9 GND QD20 QD27 QWEX VDDT QA0 A9 A10 A11 A12 A13 A14 A15 A16 B9 B10 B11 B12 B13 B14 B15 B16 C9 C10 C11 C12 C13 C14 C15 C16 QA8 QA12 NC4 JTRSTX JTDO JTMS JSO4 JSO1 QA7 VDDT NC3 JSO5 JHIGHZ JTDI GND MA0 QA6 QA11 QDQPAR JSO3 VDD33 JCLKBYP JTCK MA1 A17 A18 A19 A20 A21 A22 A23 A24 B 1-29 MA6 NC5 MCSX MDECC3 MDECC8 MD129 MD128 MD127 MA7 MDCLK MWEX VDD33 MD121 MD120 MD119 GND VDD33 MBA1 MRASX MDECC4 MD114 MD113 VDD33 MD112 A25 A26 A27 A28 A29 MD126 MD125 MD124 MD123 MD122 B17 B18 B19 B20 B21 B22 B23 B24 C 1-29 B25 B26 B27 B28 B29 MD118 MD117 MD116 VDD33 MD115 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 MD111 MD110 GND MD109 MD108 03 60 CHAPTER 2: SIGNAL DESCRIPTIONS Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN D 1-29 FUNCTION PIN FUNCTION D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8 QD3 QD8 QD13 QD19 QD26 QD31 QACLKO QNQRDY QD2 GND QD12 QD18 QD25 GND QBCLKI QARDY QD1 QD7 VDDT QD17 QD24 QD30 VDDT QDPH D9 D10 D11 D12 D13 D14 D15 D16 E9 E10 E11 E12 E13 E14 E15 E16 F9 F10 F11 F12 F13 F14 F15 F16 QA5 QA10 QA16 GND JSO2 JSO0 JSE MA2 QA4 GND QA15 CCLK7 CCLK5 CCLK2 VDD33 MA3 QA3 QA9 QA14 CCLK6 CCLK4 CCLK1 SCLKX MA4 D17 D18 D19 D20 D21 D22 D23 D24 E 1-29 MA8 GND MCASX MDECC5 MD107 MD106 MD105 MD104 MA9 MBA0 MDECC0 GND MD98 MD97 MD96 GND MA10 MDQML MDECC1 MDECC6 MD91 MD90 VDD33 MD89 D25 D26 D27 D28 D29 MD103 MD102 MD101 MD100 MD99 Freescale Semiconductor, Inc... E17 E18 E19 E20 E21 E22 E23 E24 F 1-29 E25 E26 E27 E28 E29 MD95 MD94 MD93 GND MD92 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 MD88 MD87 VDD33 MD86 MD85 C Signals Grouped by Pin Number 61 Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN G 1-29 FUNCTION PIN FUNCTION G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 J1 J2 J3 J4 J5 J6 J7 J8 QD0 QD6 QD11 QD16 QD23 TD0 TD1 TD2 TD5 TD6 TD7 TD8 TD9 TD10 TD11 TD12 TD14 VDDT TD15 TD16 TD17 GND TD18 TD19 G9 G10 G11 G12 G13 G14 G15 G16 H9 H10 H11 H12 H13 H14 H15 H16 J9 J10 J11 J12 J13 J14 J15 J16 TD3 TD4 QA13 CPREF CCLK3 CCLK0 SCLK MA5 TD13 VDDT GND VDD33 GND VDD33 GND VDD33 TD20 GND VDDT GND VDD GND VDD GND G17 G18 G19 G20 G21 G22 G23 G24 H 1-29 MA11 MDQM MDECC2 MDECC7 MD84 MD83 MD82 MD81 GND VDD33 GND VDD33 MD75 MD74 MD73 MD72 VDD GND VDD GND MD66 MD65 MD64 GND G25 G26 G27 G28 G29 MD80 MD79 MD78 MD77 MD76 Freescale Semiconductor, Inc... H17 H18 H19 H20 H21 H22 H23 H24 J 1-29 H25 H26 H27 H28 H29 MD71 MD70 MD69 MD68 MD67 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 MD63 MD62 MD61 VDD33 MD60 03 62 CHAPTER 2: SIGNAL DESCRIPTIONS Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN K 1-29 FUNCTION PIN FUNCTION K1 K2 K3 K4 K5 K6 K7 K8 L1 L2 L3 L4 L5 L6 L7 L8 M1 M2 M3 M4 M5 M6 M7 M8 TD21 TD22 GND TD23 TD24 TD25 VDDT TD26 TD28 TD29 TD30 TD31 TD32 TD33 TD34 TD35 TD37 TD38 TD39 TD40 TD41 TD42 TD43 TD44 K9 K10 K11 K12 K13 K14 K15 K16 L9 L10 L11 L12 L13 L14 L15 L16 M9 M10 M11 M12 M13 M14 M15 M16 TD27 VDDT GND VDD GND VDD GND VDD TD36 GND VDD GND VDD GND VDD GND TD45 VDDT GND VDD GND VDD GND VDD K17 K18 K19 K20 K21 K22 K23 K24 L 1-29 GND VDD GND VDD33 MD59 MD58 VDD33 MD57 VDD GND VDD GND MD52 MD51 MD50 MD49 GND VDD GND VDD33 MD43 MD42 MD41 MD40 K25 K26 K27 K28 K29 MD56 MD55 GND MD54 MD53 Freescale Semiconductor, Inc... L17 L18 L19 L20 L21 L22 L23 L24 M 1-29 L25 L26 L27 L28 L29 MD48 MD47 MD46 MD45 MD44 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 MD39 MD38 MD37 MD36 MD35 C Signals Grouped by Pin Number 63 Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN N 1-29 FUNCTION PIN FUNCTION N1 N2 N3 N4 N5 N6 N7 N8 P1 P2 P3 P4 P5 P6 P7 P8 R1 R2 R3 R4 R5 R6 R7 R8 TD46 GND TD47 TD48 TD49 VDDT TD50 TD51 TD53 TD54 VDDT TD55 TD56 TD57 GND TD58 TCLKI TPAR0 TPAR1 TPAR2 TPAR3 TD60 TD61 TD62 N9 N10 N11 N12 N13 N14 N15 N16 P9 P10 P11 P12 P13 P14 P15 P16 R9 R10 R11 R12 R13 R14 R15 R16 TD52 GND VDDT GND VDD GND VDD GND TD59 VDDT GND VDD GND VDD GND VDD TD63 GND VDD GND VDD GND VDD GND N17 N18 N19 N20 N21 N22 N23 N24 P 1-29 VDD GND VDD GND MD34 MD33 MD32 VDD33 GND VDD GND VDD33 MD27 MD26 GND MD25 VDD GND VDD GND MD20 MD19 MD18 MD17 N25 N26 N27 N28 N29 MD31 MD30 MD29 GND MD28 Freescale Semiconductor, Inc... P17 P18 P19 P20 P21 P22 P23 P24 R 1-29 P25 P26 P27 P28 P29 MD24 MD23 VDD33 MD22 MD21 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 MD16 MD15 MD14 MD13 MD12 03 64 CHAPTER 2: SIGNAL DESCRIPTIONS Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN T 1-29 FUNCTION PIN FUNCTION T1 T2 T3 T4 T5 T6 T7 T8 U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8 TA0 TCE0X TCE1X TCE2X TCE3X TWE0X TWE1X TWE2X TA1 VDDT TA2 TA3 TA4 GND TA5 TA6 TA8 TA9 GND TA10 TA11 TA12 VDDT TA13 T9 T10 T11 T12 T13 T14 T15 T16 U9 U10 U11 U12 U13 U14 U15 U16 V9 V10 V11 V12 V13 V14 V15 V16 TWE3X VDDT GND VDD GND VDD GND VDD TA7 GND VDD GND VDD GND VDD GND TA14 VDDT GND VDD GND VDD GND VDD T17 T18 T19 T20 T21 T22 T23 T24 U 1-29 GND VDD GND VDD33 MD11 MD10 MD9 MD8 VDD GND VDD GND MD2 MD1 MD0 GND GND VDD GND VDD33 CPF_2 CPF_1 VDD33 CPF_0 T25 T26 T27 T28 T29 MD7 MD6 MD5 MD4 MD3 Freescale Semiconductor, Inc... U17 U18 U19 U20 U21 U22 U23 U24 V 1-29 U25 U26 U27 U28 U29 CPF_6 CPF_5 CPF_4 VDD33 CPF_3 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 CPE_6 CPE_5 GND CPE_4 CPE_3 C Signals Grouped by Pin Number 65 Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN W 1-29 FUNCTION PIN FUNCTION W1 W2 W3 W4 W5 W6 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 TA15 TA16 TA17 TA18 TA19 TA20 TA21 XPUHOT SPDO SPDI SPLD SPCK SICL SIDA PGNTX PIDSEL PSERRX GND PPERRX PDEVSELX PSTOPX VDD33 PCLK PRSTX W9 W10 W11 W12 W13 W14 W15 W16 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 PFRAMEX GND VDD GND VDD GND VDD GND PINTA VDDT GND VDD GND VDD GND VDD PREQX GND VDD GND VDD GND VDD GND W17 W18 W19 W20 W21 W22 W23 W24 Y 1-29 VDD GND VDD GND CPE_2 CPE_1 CPE_0 CPD_6 GND VDD GND VDD33 CPD_0 CPC_6 CPC_5 CPC_4 VDD GND VDD GND CPB_5 CPB_4 CPB_3 VDD33 W25 W26 W27 W28 W29 CPD_5 CPD_4 CPD_3 CPD_2 CPD_1 Freescale Semiconductor, Inc... Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 AA 1-29 Y25 Y26 Y27 Y28 Y29 CPC_3 CPC_2 CPC_1 CPC_0 CPB_6 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 CPB_2 CPB_1 CPB_0 GND CPA_6 03 66 CHAPTER 2: SIGNAL DESCRIPTIONS Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN AB 1-29 FUNCTION PIN FUNCTION AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 PPAR PCBEX3 VDD33 PCBEX2 PCBEX1 PCBEX0 GND PIRDYX PAD31 PAD30 PAD29 PAD28 PAD27 FRXCLK FRXCTL2 FIN28 PAD26 PAD25 PAD24 PAD23 PAD22 FRXCTL6 FRXCTL1 FIN27 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 PTRDYX VDD33 GND VDDF GND VDDF GND VDDF FIN21 FIN14 FIN9 FIN2 FTXCTL4 FOUT30 FOUT23 FOUT18 FIN20 FIN13 FIN8 FIN1 FTXCTL3 FOUT29 FOUT22 FOUT17 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AC 1-29 GND VDD33 GND VDD33 CPA_5 CPA_4 GND CPA_3 FOUT11 FOUT5 CP9_5 CP8_5 CP8_0 CP7_0 CP6_0 CP5_1 FOUT10 FOUT4 CP9_4 CP8_4 CP7_6 CP6_6 CP5_6 CP5_0 AB25 AB26 AB27 AB28 AB29 CPA_2 CPA_1 VDD33 CPA_0 CP9_6 Freescale Semiconductor, Inc... AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AD 1-29 AC25 AC26 AC27 AC28 AC29 CP4_3 CP3_3 CP2_3 CP1_4 CP0_6 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 CP4_2 CP3_2 CP2_2 CP1_3 CP0_5 C Signals Grouped by Pin Number 67 Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN AE 1-29 FUNCTION PIN FUNCTION AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 PAD21 GND PAD20 PAD19 PAD18 VDDF FRXCTL0 FIN26 PAD17 PAD16 VDD33 PAD15 PAD14 FRXCTL5 GND FIN25 PAD13 PAD12 PAD11 PAD10 PAD9 FRXCTL4 FIN31 FIN24 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 FIN19 GND FIN7 FIN0 FTXCTL2 FOUT28 VDDF FOUT16 FIN18 FIN12 FIN6 GND FTXCTL1 FOUT27 FOUT21 FOUT15 FIN17 FIN11 FIN5 FTXCLK VDDF FOUT26 FOUT20 FOUT14 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AF 1-29 FOUT9 FOUT3 CP9_3 GND CP7_5 CP6_5 CP5_5 VDD33 FOUT8 GND CP9_2 CP8_3 CP7_4 CP6_4 GND CP4_6 VDDF FOUT2 CP9_1 CP8_2 CP7_3 CP6_3 CP5_4 CP4_5 AE25 AE26 AE27 AE28 AE29 CP4_1 CP3_1 CP2_1 GND CP0_4 Freescale Semiconductor, Inc... AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AG 1-29 AF25 AF26 AF27 AF28 AF29 CP4_0 CP3_0 VDD33 CP1_2 CP0_3 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 CP3_6 CP2_6 CP2_0 CP1_1 CP0_2 03 68 CHAPTER 2: SIGNAL DESCRIPTIONS Table 32 Signals Listed by Pin Number (continued) PIN FUNCTION PIN FUNCTION PIN AH 1-29 FUNCTION PIN FUNCTION AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 PAD8 VDD33 PAD7 PAD6 PAD5 GND FIN30 FIN23 PAD4 PAD3 PAD2 PAD1 PAD0 FRXCTL3 FIN29 FIN22 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 FIN16 VDDF FIN4 FTXCTL6 FTXCTL0 FOUT25 GND FOUT13 FIN15 FIN10 FIN3 FTXCTL5 FOUT31 FOUT24 FOUT19 FOUT12 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AJ 1-29 FOUT7 FOUT1 CP9_0 VDD33 CP7_2 CP6_2 CP5_3 GND FOUT6 FOUT0 CP8_6 CP8_1 CP7_1 CP6_1 CP5_2 CP4_4 AH25 AH26 AH27 AH28 AH29 CP3_5 CP2_5 CP1_6 VDD33 CP0_1 Freescale Semiconductor, Inc... AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 CP3_4 CP2_4 CP1_5 CP1_0 CP0_0 C JTAG Support 69 JTAG Support The C-5e NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All required public instructions are implemented, as well as some optional instructions. This section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types. Pinout Freescale Semiconductor, Inc... The C-5e NP uses the standard JTAG pins including the optional test reset pin. Table 30 describes the pins and their functions. The C-5e NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in Table 33. Table 33 JTAG Internal Register Descriptions REGISTER NAME REGISTER LENGTH DESCRIPTION JTAG Data Registers Bypass Boundary Device Identification 1 1549 32 Standard JTAG bypass register Boundary Scan Register Standard JTAG IDCODE Register Boundary Scan Restriction Boundary Scan Cell Types SCLK/SCLKX inputs must not toggle when exercising the boundary scan function for JTAG. The C-5e NP boundary scan register contains only two cell types. All input cells are observe only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE 1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in Figure 8. 03 70 CHAPTER 2: SIGNAL DESCRIPTIONS Figure 7 Observe-Only Cell To next cell From System Pin G1 To System Logic Freescale Semiconductor, Inc... 0 1 From last cell Shift DR Clock DR 1D C1 Figure 8 Cell Design That Can Be Used for Both Input and Output Pins Node To next cell G1 0 1 G1 0 1 From last cell Clock DR From/To System Shift DR To/From System Pin 1D C1 1D C1 Update DR C JTAG Support 71 IDcode Register The C-5e NP implements a standard 32bit JTAG identification register. Table 34 lists the value of the code for full identification and its subcomponents. Table 34 JTAG Identification Code and Its Subcomponents FIELD NAME WIDTH BIT POSITIONS BINARY VALUE Version 4 16 11 1 31-28 27-12 11-1 0 0000 0000_0000_0010_0001 001_1001_0110 1 Freescale Semiconductor, Inc... Part Number Manufacturer Identity LSB The concatenated 32bit value is hexidecimal 0002132d. JTAG Instruction Register The C-5e NP contains a 4bit instruction register. Table 35 lists the instructions that are supported. Table 35 Instruction Register Instructions INSTRUCTION MNEMONIC SELECTED REGISTER INSTRUCTION OPCODE Extest Idcode Sample/Preload Highz Clamp Bypass Reserved* Reserved* Bypass Bypass Bypass Bypass Bypass Bypass Boundary Scan Identification Register Boundary Scan Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 03 72 CHAPTER 2: SIGNAL DESCRIPTIONS Table 35 Instruction Register Instructions (continued) INSTRUCTION MNEMONIC SELECTED REGISTER INSTRUCTION OPCODE Bypass Bypass * Bypass Register Bypass Register 1110 1111 There are two reserved instructions intended for Motorola Corporation's internal use. These should not be programmed by users. Freescale Semiconductor, Inc... Boundary Scan Description Language In order to simplify board test, Motorola Corporation has provided a boundary scan description language (BSDL) file (c5e.bsdl) in the Motorola web site that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. http://www.motorola.com/networkprocessors C C5ENPA1-DS/D Chapter 3 Rev 03 ELECTRICAL SPECIFICATIONS Freescale Semiconductor, Inc... Absolute Maximum Ratings Table 36 lists the absolute maximum ratings for the C-5e network processor. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" (Table 37) is possible. Exposure to conditions beyond Table 36 can: * * Reduce device reliability Result in premature device failure, even with no immediate sign of failure Prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the C-5e NP. Table 36 C-5e Network Processor Absolute Maximum Ratings PARAMETER MIN MAX UNIT VDD33/VDDT/VDDF Supply Voltage (3.3V input)* VDD Supply Voltage (1.2V input)* Voltage on any pin Static Discharge Voltage Storage Temperature Absolute Maximum Junction Temperature * -0.5 -0.5 -0.5 2000/500 -40 -40 +5 +2.2 VDD33 + 0.5 +125 +125 V V V V C C Voltages are relative to Ground 03 74 CHAPTER 3: ELECTRICAL SPECIFICATIONS Recommended Operating Conditions The recommended operating conditions describe an environment the C-5e NP network processor is expected to encounter during normal operation. Table 37 delineates the recommended operating parameters for the C-5e NP. Table 37 C-5e Network Processor Recommended Operating Conditions PARAMETER MIN NOMINAL MAX UNIT Freescale Semiconductor, Inc... VDD33 Supply Voltage VDDTSupply Voltage VDDFSupply Voltage VDD Supply Voltage IDD33 - VDD33 Supply Current IDD - VDD Supply Current Tj Junction Temperature * 3.135 3.135 2.375 3.135 1.14 3.3 3.3 2.5 3.3 1.2 3.465 3.465 2.625* 3.465 1.26 1.3 8.5 V V V V A A C -40 125 For FP operation with I/Os @ 2.5V nominal. For FP operation with I/Os @ 3.3V nominal. C DC Characteristics 75 DC Characteristics The DC electrical characteristics define the input operating conditions for proper operation and the output responses to applied DC signals and switch characteristics over specified voltage and temperature ranges. The DC electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. Table 38 outlines the C-5e NP DC characteristics. Table 38 C-5e Network Processor DC Characteristics PARAMETER* MIN MAX UNIT NOTES Freescale Semiconductor, Inc... LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Output High Voltage LVTTL Output Low Voltage LVTTL Input Current LVPECL Input High Voltage LVPECL Input Low Voltage LVPECL Output High Voltage LVPECL Output Low Voltage LVPECL Input Current CPREF * 2.0 -0.3 2.4 VDD33+.3 0.8 0.4 V V V V @IOH = -2mA @IOL = +2mA VIN = 0V or VDD33 -100 VDD33 -1.165 -0.3 VDD33 -1.025 VDD33 -2.20 -100 VDD33 -1.38 +100 VDD33+.3V VDD33 -1.475 VDD33 -0.60 VDD33 -1.620 +100 VDD33 -1.26 A V V V V Load = 50ohm to VDD33 - 2V Load = 50ohm to VDD33 - 2V Single-ended LVPECL reference A V All voltages are relative to Ground unless otherwise indicated. Each control input pin has a capacitance associated with it. The capacitance at the control input is due to the package and the input circuitry connected to the pin. Capacitance is based on these conditions: TA = 25C; VDD33 = 3.3V; f = 1MHz. Table 39 provides capacitance data. Table 39 C-5e Network Processor Capacitance Data PARAMETER TYPICAL UNIT All Pins 5 pF 03 76 CHAPTER 3: ELECTRICAL SPECIFICATIONS Power Sequencing It is intended that the VDD33/VDDT/VDDF and VDD rails are sequenced to their final value together for most applications. VDD33, VDDT and VDDF must be above VDD at all times. VDD must be brought to its final value within 100ms of sequencing on VDD33, VDDT and VDDF. It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running or begin running during power sequencing to propagate reset inside the C-5e NP. Figure 9 indicates the relationship between the clocks and PRSTX. There is no requirement that the asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be asserted within 100s of power initiation. Typically, reset is held low during power initiation. Figure 9 Bringup Clock Timing Diagram Freescale Semiconductor, Inc... VDD, VDD33, VDDT, VDDF 100s PRSTX )( 1ms TCLKI, PCLK, SCLK, SCLKX, MDCLK, FTXCLK, FRXCLK 100s )( C Power and Thermal Characteristics 77 Power and Thermal Characteristics Table 40 provides the derived power and thermal characteristics for the production version of the C-5e NP. Table 40 C-5e Network Processor Power and Thermal Characteristics PARAMETER MIN TYP MAX UNITS TEST CONDITIONS Freescale Semiconductor, Inc... Power Dissipation, PD Maximum Junction Temperature, TJ Thermal Resistance, junction to case, JC Thermal Resistance, junction to printed circuit board, JB 5.5 9.2 13.0 125 W oC oC/W oC/W 266MHz core clock See Note below See Note below See Note below See Note below <0.1 4.8 Table 40 note: Power dissipation values assume the following conditions: * * * * * * * Thermal Management Information BMU memory operating at 133MHz. TLU memory operating at 133MHz. QMU operating at 175MHz. VDD = 1.2V, VDD33 = 3.3V, TJ at approximately 50C for typical values. VDD and VDD33 are 5% higher for maximum values. "Minimum" PD based on idle condition (clocks running and no programs executing). "Typical" PD based on test application that implements Fast Ethernet forwarding actively running on all CPs. "Maximum" PD based on maximum consumption for any high-bandwidth communications application executing on all CPs, FP, and XP. This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods--spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (refer to Figure 10); however, due to the potential 03 78 CHAPTER 3: ELECTRICAL SPECIFICATIONS large mass of the heat sink, attachment through the printed circuit board is suggested. If a spring clip is used, the spring force should not exceed 5.5 pounds. Figure 10 Package Cross Section View with Several Heat Sink Options Heat Sink Freescale Semiconductor, Inc... Heat Sink Clip Thermal Interface Material CBGA Package Printed Circuit Board Internal Package Conduction Resistance For the exposed-die packaging technology the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case (or top-of-die for exposed silicon) thermal resistance The die junction-to-ball thermal resistance Figure 11 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. C Power and Thermal Characteristics 79 Figure 11 Package with Heat Sink Mounted to the Printed Circuit Board External Resistance Radiation Convection Heat Sink Freescale Semiconductor, Inc... Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed Circuit Board (PCB) External Resistance Radiation Convection Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by convection. Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: T j = T a + T r + (jc + int + sa ) x P d where: T j is the die-junction temperature T a is the inlet cabinet ambient temperature T r is the air temperature rise within the computer cabinet 03 80 CHAPTER 3: ELECTRICAL SPECIFICATIONS jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance P d is the power dissipated by the device During operation, the die-junction temperatures (T j ) should be maintained less than the value specified in Table 40. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a ) may range from 30 to 40C. The air temperature rise within a cabinet (T r ) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (int ) is typically about 1.5C/W. For example, assuming a T a of 30C, a T r of 5C, a CBGA package jc = 0.1, and a maximum power consumption (P d ) of 13.0 W, the following expression for T j is obtained: Die-junction temperature: T j = 30C + 5C + (0.1C/W + 1.5C/W + sa ) x 13.0 W For this example, a sa value of 5.3C/W or less is required to maintain the die junction temperature below the maximum value of Table 40. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. Freescale Semiconductor, Inc... C AC Timing Specifications 81 AC Timing Specifications AC timing specifications consist of input requirements and output responses. The input requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal. The AC timing specifications are defined separately for each interface to the C-5e NP. See Figure 12. Output timing specifications for LVTTL pins are given with a 20pF load on the output. Other loads can be simulated with the IBIS model available from Motorola. The LVPECL driver is specified into a 50 load terminated to a (VDD33 - 2V) reference. Figure 12 Test Loading Conditions LVTTL DUT 20pF Freescale Semiconductor, Inc... VDD33 +2V LVPECL DUT 50 03 82 CHAPTER 3: ELECTRICAL SPECIFICATIONS Clock Timing Specifications Cycle 1 SCLK SCLKX Tsc Tsh Tsl The system clock timing is shown in Figure 13 and described in Table 41. Figure 13 System Clock Timing Diagram Cycle 2 Cycle 3 Cycle 4 Cycle 5 Freescale Semiconductor, Inc... CCLKn TccN Tcch Tccl Table 41 System Clock Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tsc Tsh Tsl Tcc0 Tcc1 Tcc2 Tcc3 Tcc4 Tcc5 Tcc6 Tcc7 Tcch Tccl * System Cycle Time 3.76 Sys Clk High Pulse Sys Clk Low Pulse CCLK0 Cycle Time CCLK1 Cycle Time CCLK2 Cycle Time CCLK3 Cycle Time CCLK4 Cycle Time CCLK5 Cycle Time CCLK6 Cycle Time CCLK7 Cycle Time CCLKm High Time CCLKm Low Time 40% 40% 45 45 647.67 488.28 29.097 22.353 20.00 9.412 8.00 6.43 60% 60% 55 55 ns 266MHz core clock Duty cycle* Duty cycle* ns ns ns ns ns ns ns ns T1 E1 E3 T3 RMII Fibre Channel GMII OC-3 % cycle pulse is high % cycle pulse is low Pulse duty cycle measured at crossing voltage of SCLK/SCLKX C AC Timing Specifications 83 The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5e NP. It is also possible to use one or more CCLKn inputs for other frequencies; contact your Motorola representative for more information. CP Timing Specifications This section describes the timing for the following CP interfaces: Freescale Semiconductor, Inc... * * * * * DS1/DS3 10/100 Ethernet Gigabit Ethernet OC-3 OC-12 DS1/DS3 Timing Specifications The DS1/DS3 interface timing is shown in Figure 14 and described in Table 42. Figure 14 DS1/DS3 Ethernet Timing Diagram Cycle 1 CPn_0 (TCLK) Tcdt CPn_2/3 (Tx) Tcdo Cycle 2 CPn_1 (RCLK) Tcdr CPn_4/5 (Rx) Tcds Tcdh Cycle 3 Cycle 4 Cycle 5 Cycle 2 Cycle 3 Cycle 4 Cycle 5 03 84 CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 42 DS1/DS3 Ethernet Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tcdt Tcdo Tcdr Tcds Tcdh DS1/DS3 Transmit Cycle Time DS1/DS3 Output Time DS1/DS3 Receive Cycle Time DS1/DS3 Setup Time DS1/DS3 Hold Time 2.0 0 3.0/3.0 647/22.4 400/15.0 647/22.4 ns ns ns ns ns Freescale Semiconductor, Inc... 10/100 Ethernet Timing Specifications The 10/100 Ethernet interface timing is shown in Figure 15 and described in Table 43. Figure 15 10/100 Ethernet Timing Diagram Cycle 1 CPn_0 (TCLK) Tcet CPn_2/3/6 (Tx) Tceo CPn_1/4/5 (Rx) Tces Tceh Cycle 2 Cycle 3 Cycle 4 Cycle 5 Table 43 10/100 Ethernet Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tcet Tceo Tces Tceh * Transmit Cycle Time* Output Time Setup Time Hold Time 3.0 2.0 0 20 15.0 ns ns ns ns STD/Fast Ethernet C AC Timing Specifications 85 Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in Table 44. The TBI interface timing is shown in Figure 16 and described in Table 45. Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram GMII / TBI Tx Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Freescale Semiconductor, Inc... CPn_0 (TCLK) Tcgt CPn_2-6 (Tx) CPn+1_2-6 (Tx) Tcgo MII Tx MII CPn_1 (TCLKI) Cycle 1 Cycle 2 Cycle 3 Tcmt MII CPn_2-6 (Tx) Tcmo TBI Rx CPn+2_1 (RCLK) CPn+3_1 (RCLKN) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Tctr Tctd CPn+2_2-6 (Rx) CPn+3_2-6 (Rx) Tcts Tcth GMII/MII Rx CPn+2_1 (RCLK) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Tcgr CPn+2_2-6 (Rx) CPn+3_1-6 (Rx) Tcgs Tcgh 03 86 CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 44 Gigabit GMII/MII Ethernet Interface Timing Description SYMBOL GIGABIT PARAMETER MIN TYP MAX UNIT COMMENT Tcgt Tcgo Tcgr Transmit Cycle Time, GMII Output Time, GMII Receive Cycle Time Setup Time Hold Time Transmit Cycle Time, MII Output Time, MII 2 2.0 0.0 3.0 8.0 6.0 8.0 ns ns ns ns ns Freescale Semiconductor, Inc... Tcgs Tcgh Tcmt Tcmo 40/400 8 ns ns 100BaseT/10BaseT Table 45 Gigabit TBI Interface Timing Description SYMBOL TBI PARAMETER MIN TYP MAX TOL UNIT Tctt Tcto Tctr Tctd Tcts Tcth * Transmit Cycle Time Output Time Receive Cycle Time Rclk/Rclkn Deviation Setup Time Hold Time 2.0 0.0 3.0 8.0 6.0* 16.0 1.0 ns ns ns ns ns ns For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns. C AC Timing Specifications 87 OC-3 Timing Specifications The OC-3 interface timing is shown in Figure 17 and described in Table 46. Figure 17 OC-3 Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Freescale Semiconductor, Inc... CPn_2 Tc3t CPn_3 Tc3i Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 CPn_0 CPn_1 Tc3r Tc3d CPn_4 Tc3s Tc3h CPn_5 Tc3s Tc3h Table 46 OC-3 Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tc3t Tc3i Tc3r Tc3d Tc3s Tc3h * OC-3 Transmit Cycle Time OC-3 Pulse Width OC-3 Receive Cycle Time* OC-3 Clock Duty Cycle OC-3 Setup Time OC-3 Hold Time 6.43 2.0 6.0 40 2.0 0.0 ns ns ns 60 % ns ns 155.52MHz 03 88 CHAPTER 3: ELECTRICAL SPECIFICATIONS OC-12 Timing Specifications The OC-12 interface timing is shown in Figure 18 and described in Table 47. Figure 18 OC-12 Timing Diagram Cycle 1 CPn_1 (TCLKI) Tc12i Cycle 2 Cycle 3 Cycle 4 Cycle 5 Freescale Semiconductor, Inc... Tc12d CPn_0 (TCLK) Tc12t CPn+1_2-5 (Tx) Tc12o Cycle 1 Cycle 2 Cycle 3 CPn_1 (RCLK) Tc12r CPn+2_2-6 (Rx) CPn+3_2-5 (Rx) Tc12s Tc12h Table 47 OC-12 Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tc12i Tc12d Tc12t Tc12o Tc12r Tc12s Tc12h * OC-12 Transmit Cycle Time* OC-3 Clock Duty Cycle OC-12 Transmit Cycle Time OC-12 Output Time OC-12 Receive Cycle Time OC-12 Setup Time OC-12 Hold Time 12.86 40 12.86 3.0 12.0 2.0 0.0 ns 60 10.0 % ns ns ns ns ns 12.86 Input from PHY Output from C-5e NP Aligned to TCLK C AC Timing Specifications 89 Executive Processor Timing Specifications The XP timing specifications include: Freescale Semiconductor, Inc... * * * * PCI Timing Specifications MDIO Serial Interface Timing Specifications Low Speed Serial Interface Timing Specifications PROM Interface Timing Specifications PCI Timing Specifications The PCI timing is shown in Figure 19 and described in Table 48. Figure 19 PCI Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 PCLK Tpc PAD/P_ctl (output) Tpao PAD/P_ctl (input) Tpas PGNTX (input) Tpgs PIDSEL (input) Tpis Tpih Tpgh Tpah Tpaz Tpav 03 90 CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 48 PCI Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tpc Tpas Tpah Tpao Tpaz Tpav Tpgs Tpgh Tpis Tpih PCI Cycle Time* PAD/P_ctl Setup PAD/P_ctl Hold PAD/P_ctl Output PAD/P_ctl Clk to Tri PAD/P_ctl Clk to Driven PGNTX Setup PGNTX Hold PIDSEL Setup PIDSEL Hold PRSTX** PINTA** 15.0 3.0 0.0 2.0 2.0 2.0 5.1 0.0 3.0 0.0 6.0 6.0 6.0 ns ns ns ns ns ns ns ns ns ns ns ns Freescale Semiconductor, Inc... * 66MHz PCI P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX Not fully tested, values based on design/characterization. ** Asynchronous C AC Timing Specifications 91 MDIO Serial Interface Timing Specifications The MDIO serial interface timing is shown in Figure 20 and described in Table 49. Figure 20 MDIO Serial Interface Timing Diagram Cycle 2 Cycle 3 Cycle 4 Freescale Semiconductor, Inc... SICL Tsic SIDA (output) Tsods SIDA (input) Tsids Tsodh Table 49 MDIO Serial Interface Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tsic Tsids Tsidh Tsods Tsodh SICL Cycle Time SIDA Input Setup SIDA Input Hold SIDA Output Setup SIDA Output Hold 40 10 0.0 10 10 ns ns ns ns ns 03 92 CHAPTER 3: ELECTRICAL SPECIFICATIONS Low Speed Serial Interface Timing Specifications The low speed serial interface timing is shown in Figure 21 and described in Table 50. Figure 21 Low Speed Serial Interface Timing Diagram Freescale Semiconductor, Inc... Cycle 2 Cycle 3 SICL Tslss SIDA Tslhs Tslhd Tslsd Tslc Tslst Tslb Table 50 Low Speed Serial Interface Timing Description SYMBOL PARAMETER MIN MAX UNIT Tslc Tslss Tslhs Tslsd Tslhd Tslst Tslb Cmax SICL Cycle Time Set-up Time for Repeated START Condition Hold Time START Condition Data Set-up Time Data Hold Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive load for each line of the bus 2500 600 600 250 0.0 600 1250 400 ns ns ns ns ns ns ns pF C AC Timing Specifications 93 PROM Interface Timing Specifications The PROM interface timing is shown in Figure 22 and described in Table 51. Figure 22 PROM Interface Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Freescale Semiconductor, Inc... SPCK Tspc SPDI Tspis SPLD Tsplo SPDO Tspdo Tspih Table 51 PROM Interface Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tspc Tspis Tspih Tsplo Tspdo SPCK Cycle Time SPDI Setup SPDI Hold SPLD Output SPDO Output 40.0 10.0 0.0 Tsc Tsc Tsc + 3.0 Tsc + 3.0 ns ns ns ns ns 03 94 CHAPTER 3: ELECTRICAL SPECIFICATIONS Fabric Processor Timing Specifications Cycle 1 The FP timing specifications are shown in Figure 23 and described in Table 52. Figure 23 Fabric Processor Timing Diagram Cycle 2 Cycle 3 Cycle 4 Cycle 5 FRXCLK Freescale Semiconductor, Inc... Tfrc FRXCTL (output) Tfrco Tfrcz Tfrcv FRXCTL (input) Tfrcs Tfrch FINn Tfrds Tfrdh FTXCLK Tftc FTXCTL (output) Tftco Tftcz Tftcv FTXCTL (input) Tftcs FOUTn Tftdo Tftch C AC Timing Specifications 95 Table 52 Fabric Processor Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tfrc Tfrcs Tfrch Tfrco Tfrcz Tfrcv Tfrds Tfrdh Tftc Tftcs Tftch Tftco Tftcz Tftcv Tftdo * FRX Cycle Time FRXCTL Setup FRXCTL Hold FRXCTL Output FRXCTL Clk to Tri* FRXCTL Clk to Driven* FIN Setup FIN Hold FTX Cycle Time FTXCTL Setup FTXCTL Hold FTXCTL Output FTXCTL Clk to Tri* FTXCTL Tri to Driven* FOUT Output 8.0 4.0 1.5 0.0 1.0 1.0 1.0 4.0 1.5 0.0 8.0 4.0 1.5 0.0 1.0 1.0 1.0 1.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Utopia2 Mode All other modes Utopia2 Mode All other modes Utopia2 Mode All other modes Freescale Semiconductor, Inc... Not fully tested, values based on design/characterization. 03 96 CHAPTER 3: ELECTRICAL SPECIFICATIONS BMU Timing Specifications The BMU timing specifications are shown in Figure 24 and described in Table 53. The BMU synchronous DRAM interface is PC100-compliant and designed to work with industry standard SDRAM components with 12 or fewer address lines. The information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in SDRAM data sheets. Figure 24 BMU Timing Diagram Freescale Semiconductor, Inc... Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 MDCLK Tmc M_ctl Tmco MAn Tmao MDn (output) Tmdo MDn (input) Tmds Tmdh Tmdz Tmdv Table 53 BMU Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tmc Tmco Tmao Tmds Tmdh Tmdo Tmdz Tmdv * BMU Cycle Time BMU Ctrl Output BMU Addr Output BMU Data Setup BMU Data Hold BMU Data Output BMU Data Clk to Tri* BMU Data Clk to Driven* 7.5 0.8 0.8 0.5 1.1 0.8 0.8 0.8 4.0 4.0 4.0 3.4 3.4 ns ns ns ns ns ns ns ns Not fully tested, values based on design/characterization. C AC Timing Specifications 97 Table 54 Signal Groups in BMU Timing Diagrams SIGNAL GROUP INCLUDED SIGNALS Control (M_ctl) Address (MAn) Data (MDn) MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM, MDQML MA0 - MA11 MD0 - MD129, MDECC0 - MDECC8 Freescale Semiconductor, Inc... 03 98 CHAPTER 3: ELECTRICAL SPECIFICATIONS TLU Timing Specifications The TLU timing specifications are shown in Figure 25 and described in Table 55. Figure 25 TLU Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 TCLKI Freescale Semiconductor, Inc... Ttc T_ctl Ttco TAn Ttao TDn (output) Ttdo TDn (input) Ttds Ttdh Ttdz Ttdv Table 55 TLU Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Ttc Ttco Ttao Ttds Ttdh Ttdo Ttdz Ttdv * TLU Cycle Time TLU Ctrl Output TLU Addr Output TLU Data Setup TLU Data Hold TLU Data Output TLU Data Clk to Tri* TLU Data Clk to Driven* 7.5 0.8 0.8 1.0 1.2 0.8 0.8 0.8 3.7 3.7 3.7 3.4 3.4 ns ns ns ns ns ns ns ns Not fully tested, values based on design/characterization. Table 56 Signal Groups in TLU Timing Diagrams SIGNAL GROUP INCLUDED SIGNALS Control (T_ctl) Address (TAn) TCE0X - TCE3X, TWE0X - TWE3X TA0 - TA21 C AC Timing Specifications 99 Table 56 Signal Groups in TLU Timing Diagrams SIGNAL GROUP INCLUDED SIGNALS Data (TDn) TD0 - TD63, TPAR0-3 Freescale Semiconductor, Inc... QMU SRAM (Internal Mode) Timing Specifications The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and described in Table 57. Figure 26 QMU SRAM (Internal Mode) Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 QACLKI Tqc Q_ctl Tqco QAn Tqao QDn (output) Tqdo QDn (input) Tqds Tqdh Tqdz Tqdv 03 100 CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 57 QMU SRAM (Internal Mode) Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tqc Tqco Tqao QMU Cycle Time QMU Ctrl Output QMU Addr Output QMU Data Setup QMU Data Hold QMU Data Output 5.7 0.8 0.8 0.8 0.8 0.9 3.4 3.4 3.4 3.4 3.4 ns ns ns ns ns ns ns ns Loading is 50 transmission line. Loading is 50 transmission line. Loading is 50 transmission line. Freescale Semiconductor, Inc... Tqds Tqdh Tqdo Tqdz Tqdv * QMU Data Clk to Tri* 0.9 QMU Data Clk to Driven* 0.9 Not fully tested, values based on design/characterization. Table 58 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams SIGNAL GROUP INCLUDED SIGNALS Control (Q_ctl) Address (QAn) Data (QDn) QWEX QA0-QA16 QD0-QD31, QDPL, QDPH C AC Timing Specifications 101 QMU to Q-5 (External Mode) Timing Specifications The QMU to Q-5 (External Mode) timing specifications are shown in Figure 27 and describded in Table 59. Figure 27 QMU to Q-5 (External Mode) Timing Diagram Cycle 1 Cycle 2 Freescale Semiconductor, Inc... Tqec QACLKI Tqep QBCLKI Tqep Tqec DQDATA Tqeh Tqes Tqeh Tqes Tqec QACLKO Tqep QBCLKO Tqep Tqec NQDATA Tqeomax Tqeomax Tqeomin Tqeomin 03 102 CHAPTER 3: ELECTRICAL SPECIFICATIONS Table 59 QMU to Q-5 (External Mode) Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT Tqec QMU External Cycle Time 10.0 ns QACLKO/QBCLKO derived from QACLKI/QBCLKI Tqep Freescale Semiconductor, Inc... QMU CLKA-CLKB delta between rising edges QMU Input Data Setup QMU Input Data Hold QMU Data Output 4.8 0.6 0.8 -.85 1.3 ns ns ns ns Determines valid time for data from each clock rising edge Tqes Tqeh Tqeo Table 60 Signal Groups in QMU to Q-5 (External Mode) Timimg Diagrams SIGNAL GROUP INCLUDED SIGNALS Input Clocks (QnCLKI) Output Clocks (QnCLKO) Input Data (DQDATA) Output Data (NQDATA) QACLKI, QBCLKI QACLKO, QBCLKO QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR QA0-16, QWEX, QD24-31 C C5ENPA1-DS/D Chapter 4 Rev 03 MECHANICAL SPECIFICATIONS Freescale Semiconductor, Inc... Package Views The C-5e network processor is an 840 pin (29 pins x 29 pins) Ball Grid Array (BGA) package as shown in the following illustrations. Table 61 defines the package measurements. Figure 28 C-5e Network Processor BGA Package Side View A4 A2 A3 A A1 Seating Plane HiTCE: Green ceramic is thermally matched to FR4 circuit board. 03 104 CHAPTER 4: MECHANICAL SPECIFICATIONS Figure 29 C-5e Network Processor BGA Package (Bottom View) D D1 e AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 45 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Freescale Semiconductor, Inc... e E1 E b C Package Views 105 Figure 30 C-5e Network Processor BGA Package (Top View) Probe Pad Die 1.65 1.70 Optional Capacitor Pads Freescale Semiconductor, Inc... Optional Capacitor Pads 0.7 18ARS10517D001 03 106 CHAPTER 4: MECHANICAL SPECIFICATIONS Package Measurements Table 61 defines the C-5e NP package measurements, providing nominal, minimum, and maximum sizes where appropriate. Table 61 Package Measurements (Reference Figure 28, Figure 29 and Figure 30 for Symbols) SYMBOL DEFINITION NOM. (MM) MIN. (MM) MAX. (MM) Freescale Semiconductor, Inc... A A1 A2 A3 A4 D D1 E E1 e b Overall Ball height C4 and Die Body thickness Capacitor pads Body size Ball footprint (X) Body size Ball footprint (Y) Ball pitch Ball diameter 3.26 0.70 0.86 1.7 31.00 28.00 31.00 28.00 1.00 0.70 2.97 0.6 0.82 1.55 30.80 30.80 3.55 0.8 0.9 1.85 0.6 31.20 31.20 At Motorola's discretion up to fourteen (14) capacitors may or may not be attached on the top of the package. Marking Codes Table 62 explains the marking on the C-5e NP. Table 62 C-5e Network Processor Marking Codes MARKING (EXPLANATION OF CODES) Top Bottom Pin 1 Marking Logo/Part#/Date Code N/A Chamfered Corner C Reflow 107 Reflow Typical Reflow Profile for the C-5e Switch Module comprises: 1 Follow the guidelines recommended by your solder paste supplier. Flux requirements must be met for best solderability. 2 The temperature profile should be carefully characterized to ensure uniform temperature across the board and package. Solder ball voiding may be affected by ramp rates and dwell times below and above liquids. 3 A nitrogen atmosphere is not required, but will make the process more robust. It can make a difference for marginally solderable PC board pads. 4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can be used. Freescale Semiconductor, Inc... 03 108 CHAPTER 4: MECHANICAL SPECIFICATIONS Freescale Semiconductor, Inc... C C5ENPA1-DS/D Rev 03 INDEX Freescale Semiconductor, Inc... Symbols 10/100 Ethernet (RMII) Configuration 34 10/100 Ethernet Signals 34 10/100 Ethernet Timing Description 84 10/100 Ethernet Timing Diagram 84 10/100 Ethernet Timing Specifications 84 A Absolute Maximum Ratings 73 AC Timing Specifications 81 B Block Diagram, C-5e Network Processor 20 BMU SDRAM Interface Signals 52 BMU Signal Groups 97 BMU Timing Description 96 BMU Timing Diagram 96 BMU Timing Specifications 96 Boundary Scan Cell Types 69 Boundary Scan Description Language 72 Bringup Clock Timing Diagram 76 Buffer Management Unit 24 Channel Processors 22 Channel Processors Physical Interface Signals and Pins Grouped by Clusters 33 Clock and Reference Signals 31 Clock Signals 31 Clock Timing Specifications 82 Configuration 10/100 Ethernet (RMII) 34 DS1/T1 Framer Interface 34 FibreChannel TBI 38 Gigabit Ethernet 38 Gigabit Ethernet (GMII) 35 SONET OC-12 Transceiver Interface 40 SONET OC-3 Transceiver Interface 39 Configurations GMII/TBI Transmit and Receive Pin 36 CP Timing Specifications 83 CSIX-L1 Mode, C-5e Network Processor to Fabric Interface Pin Mapping 51 D Data Registers JTAG 69 DC Characteristics 75 Description Functional 19 Description Language Boundary Scan 72 Descriptions Signal 27 Diagram 10/100 Ethernet Timing 84 BMU Timing 96 Bringup Clock Timing 76 DS1/DS3 Ethernet Timing 83 03 C C-5e Network Processor Absolute Maximum Ratings 73 C-5e Network Processor BGA Package, Bottom View 104 C-5e Network Processor BGA Package, Side View 103 C-5e Network Processor Capacitance Data 75 C-5e Network Processor DC Characteristics 75 C-5e Network Processor Power and Thermal Characteristics 77 C-5e NP Channel Processors 22 Channel Processor Interface Signals 32 110 INDEX Freescale Semiconductor, Inc... Fabric Processor Timing 94 Gigabit Ethernet (TBI) Timing 85 Low Speed Serial Interface Timing 92 MDIO Serial Interface Timing 91 OC-3 Timing 87 PCI Timing 89 Pinout 28 PROM Interface 45 PROM Interface Timing 93 QMU Timing 99 Signal Groups in BMU Timing 97 Signal Groups in QMU Timing 100 Signal Groups in TLU Timing 98 System Clock Timing 82 TLU Timing 98 Diagram, Block C-5e Network Processor 20 DS1/DS3 Ethernet Timing Description 84 DS1/DS3 Ethernet Timing Diagram 83 DS1/DS3 Timing Specifications 83 DS1/T1 Framer Interface Configuration 34 DS1/T1 Framer Interface Signals 34 Fabric Processor Interface Signals 48 Fabric Processor Timing Description 95 Fabric Processor Timing Diagram 94 Fabric Processor Timing Specifications 94 Functional Description 19 G General System Interface Signal 47 Gigabit Ethernet (GMII) Configuration 35 Gigabit Ethernet (GMII) Signals One Cluster Example 36 Gigabit Ethernet (TBI) Timing Description 86, 86 Gigabit Ethernet (TBI) Timing Diagram 85 Gigabit Ethernet and FibreChannel TBI Configuration 38 Gigabit Ethernet and FibreChannel TBI Signals Example 38 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 85 GMII/TBI Transmit and Receive Pin Configurations 36 I IDcode Register 71 Instruction Register Instructions 71 E Electrical Specifications 73 Absolute Maximum Ratings 73 Executive Processor 23 PCI 23 PROM Interface 24 Serial Bus Interface 23 System Interface Signals 42 System Interfaces 23 Executive Processor Timing Specifications 89 J JTAG Data Registers 69 JTAG Identification Code and Its Sub-components 71 JTAG Instruction Register 71 JTAG Internal Register Descriptions 69 JTAG Support Pinouts 69 L F Fabric Interface Pin Mapping CSIX-L1 Mode 51 Power X(CSIX-L0) Mode 50 PRIZMA Mode 50 Utopia2/Utopia3 ATM Mode 49 Utopia2/Utopia3 PHY Mode 49 Fabric Processor 24 Low Speed Serial Interface Timing Description 92 Low Speed Serial Interface Timing Diagram 92 Low Speed Serial Interface Timing Specifications 92 LVPECL Specifications 30 LVTTL Specifications 30 M C INDEX 111 MDIO Serial Interface Timing Description 91 MDIO Serial Interface Timing Diagram 91 MDIO Serial Interface Timing Specifications 91 Measurements C-5e Network Processor 106 Mechanical Specifications 103 Miscellaneous Test Signals for JTAG, Scan, and Internal Test Routines 58 PROM Interface Timing Description 93 PROM Interface Timing Diagram 93 PROM Interface Timing Outline 46 PROM Interface Timing Specifications 93 Q QMU Signal Groups 100 QMU SRAM (Internal Mode) Timing Diagram 99 QMU SRAM Interface Signals 55, 56 QMU Timing Description 100 QMU Timing Specifications 99 QMU to Q-5 (External Mode) Timing Diagram 101 Queue Management Unit 26 Freescale Semiconductor, Inc... N No Connection Pins 58 O OC-12 Signals 40 OC-12 Timing Description 88 OC-12 Timing Specifications 88 OC-3 Signals 39 OC-3 Timing Description 87 OC-3 Timing Diagram 87 OC-3 Timing Specifications 87 Operating Conditions, Recommended 74 R Recommended Operating Conditions 74 Register IDcode 71 JTAG Instruction 71 S P Package Measurements 106 PCI Signals 42 PCI Timing Description 90 PCI Timing Diagram 89 PCI Timing Specifications 89 Pin Descriptions Grouped by Function 30 Pin Locations 28 Pin Number Signals Groups 59 Pinout Diagram 28 Power Sequencing 76, 77 Power Supply Signals 57 Power X(CSIX-L0) Mode, Fabric Interface Pin Mapping 50 PRIZMA Mode, C-5e Network Processor to Fabric Interface Pin Mapping 50 Processor, Executive 23 Processor, Fabric 24 PROM Interface Diagram 45 PROM Interface Signals 44 Serial Interface Signals 43 Serial Port Signals 43 Signal General System Interface 47 Signal Descriptions 27 Signal Summary 27 Signals 10/100 Ethernet 34 BMU SDRAM Interface 52 Channel Processor Interface 32 Clock 31 Clock and Reference 31 DS1/T1 Framer Interface 34 Fabric Processor Interface 48 Grouped by Pin Number 59 OC-12 40 OC-3 39 PCI 42 Power Supply 57 PROM Interface 44 QMU SRAM Interface 55, 56 03 112 INDEX Freescale Semiconductor, Inc... Serial Interface 43 Serial Port 43 Test 58 TLU SRAM Interface 54 SONET OC-12 Transceiver Interface Configuration 40 SONET OC-3 Transceiver Interface Configuration 39 Specifications 10/100 Ethernet Timing 84 AC Timing 81 BMU Timing 96 Clock Timing 82 CP Timing 83 DS1/DS3 Timing 83 Electrical 73 Executive Processor Timing 89 Fabric Processor Timing 94 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 85 Low Speed Serial Interface Timing 92 MDIO Serial Interface Timing 91 Mechanical 103 OC-12 Timing 88 OC-3 Timing 87 PCI Timing 89 PROM Interface Timing 93 QMU Timing 99 TLU Timing 98 XP Timing 89 System Clock Timing Description 82 System Clock Timing Diagram 82 System Interfaces Executive Processor 23 T Table Lookup Unit 25 Test Signals 58 Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test Routines 58 Timing Outline PROM Interface 46 TLU Signal Groups 98 TLU SRAM Interface Signals 54 TLU Timing Description 98 TLU Timing Diagram 98 TLU Timing Specifications 98 Transceiver Interface Configuration SONET OC-12 40 SONET OC-3 39 Transmit and Receive Pin Combinations for Gigabit Ethernet and FibreChannel 35 U Utopia2/Utopia3 ATM Mode, C-5e Network Processor to Fabric Interface Pin Mapping 49 Utopia2/Utopia3 PHY Mode, C-5e Network Processor to Fabric Interface Pin Mapping 49 X XP Timing Specifications 89 C Freescale Semiconductor, Inc... How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. 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